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2023-09-20target/loongarch: Implement xvsadd/xvssubSong Gao
This patch includes: - XVSADD.{B/H/W/D}[U]; - XVSSUB.{B/H/W/D}[U]. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-19-gaosong@loongson.cn>
2023-09-20target/loongarch: Implement xvnegSong Gao
This patch includes: - XVNEG.{B/H/W/D}. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-18-gaosong@loongson.cn>
2023-09-20target/loongarch: Implement xvaddi/xvsubiSong Gao
This patch includes: - XVADDI.{B/H/W/D}U; - XVSUBI.{B/H/W/D}U. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-17-gaosong@loongson.cn>
2023-09-20target/loongarch: Implement xvreplgr2vrSong Gao
This patch includes: - XVREPLGR2VR.{B/H/W/D}. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-16-gaosong@loongson.cn>
2023-09-20target/loongarch: Implement xvadd/xvsubSong Gao
This patch includes: - XVADD.{B/H/W/D/Q}; - XVSUB.{B/H/W/D/Q}. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-15-gaosong@loongson.cn>
2023-09-20target/loongarch: Add avail_LASX to check LASX instructionsSong Gao
Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-14-gaosong@loongson.cn>
2023-09-20target/loongarch: check_vec support check LASX instructionsSong Gao
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230914022645.1151356-13-gaosong@loongson.cn>
2023-09-20target/loongarch: Add LASX data supportSong Gao
Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-12-gaosong@loongson.cn>
2023-09-20target/loongarch: Replace CHECK_SXE to check_vec(ctx, 16)Song Gao
Introduce a new function check_vec to replace CHECK_SXE Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-11-gaosong@loongson.cn>
2023-09-20target/loongarch: Use gen_helper_gvec_2i for 2OP + imm vector instructionsSong Gao
Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-10-gaosong@loongson.cn>
2023-09-20target/loongarch: Use gen_helper_gvec_2 for 2OP vector instructionsSong Gao
Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-9-gaosong@loongson.cn>
2023-09-20target/loongarch: Use gen_helper_gvec_2_ptr for 2OP + env vector instructionsSong Gao
Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-8-gaosong@loongson.cn>
2023-09-20target/loongarch: Use gen_helper_gvec_3 for 3OP vector instructionsSong Gao
Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-7-gaosong@loongson.cn>
2023-09-20target/loongarch: Use gen_helper_gvec_3_ptr for 3OP + env vector instructionsSong Gao
Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-6-gaosong@loongson.cn>
2023-09-20target/loongarch: Use gen_helper_gvec_4 for 4OP vector instructionsSong Gao
Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-5-gaosong@loongson.cn>
2023-09-20target/loongarch: Use gen_helper_gvec_4_ptr for 4OP + env vector instructionsSong Gao
Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-4-gaosong@loongson.cn>
2023-09-20target/loongarch: Implement gvec_*_vl functionsSong Gao
Create gvec_*_vl functions in order to hide oprsz. This is used by gvec_v* functions for oprsz 16, and will be used by gvec_x* functions for oprsz 32. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-3-gaosong@loongson.cn>
2023-09-20target/loongarch: Renamed lsx*.c to vec* .cSong Gao
Renamed lsx_helper.c to vec_helper.c and trans_lsx.c.inc to trans_vec.c.inc So LASX can used them. Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230914022645.1151356-2-gaosong@loongson.cn>
2023-08-31target/helpers: Remove unnecessary 'qemu/main-loop.h' headerPhilippe Mathieu-Daudé
"qemu/main-loop.h" declares functions related to QEMU's main loop mutex, which these files don't access. Remove the unused "qemu/main-loop.h" header. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230828221314.18435-8-philmd@linaro.org>
2023-08-31target/translate: Include missing 'exec/cpu_ldst.h' headerPhilippe Mathieu-Daudé
All these files access the CPU LD/ST API declared in "exec/cpu_ldst.h". Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230828221314.18435-4-philmd@linaro.org>
2023-08-24target/loongarch: Split fcc register to fcc0-7 in gdbstubJiajie Chen
Since GDB 13.1(GDB commit ea3352172), GDB LoongArch changed to use fcc0-7 instead of fcc register. This commit partially reverts commit 2f149c759 (`target/loongarch: Update gdb_set_fpu() and gdb_get_fpu()`) to match the behavior of GDB. Note that it is a breaking change for GDB 13.0 or earlier, but it is also required for GDB 13.1 or later to work. Signed-off-by: Jiajie Chen <c@jia.je> Acked-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230808054315.3391465-1-c@jia.je> Signed-off-by: Song Gao <gaosong@loongson.cn>
2023-08-24target/loongarch: cpu: Implement get_arch_id callbackBibo Mao
Implement the callback for getting the architecture-dependent CPU ID, the cpu ID is physical id described in ACPI MADT table, this will be used for cpu hotplug. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230824005007.2000525-1-maobibo@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn>
2023-08-24target/loongarch: Add avail_IOCSR to check iocsr instructionsSong Gao
Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20230822032724.1353391-16-gaosong@loongson.cn> Message-Id: <20230822072219.35719-1-philmd@linaro.org>
2023-08-24target/loongarch: Add avail_LSX to check LSX instructionsSong Gao
Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20230822032724.1353391-15-gaosong@loongson.cn> Message-Id: <20230822073026.35776-1-philmd@linaro.org>
2023-08-24target/loongarch: Add avail_LAM to check atomic instructionsSong Gao
Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20230822032724.1353391-14-gaosong@loongson.cn> Message-Id: <20230822071959.35620-8-philmd@linaro.org>
2023-08-24target/loongarch: Add avail_LSPW to check LSPW instructionsSong Gao
Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20230822032724.1353391-13-gaosong@loongson.cn> Message-Id: <20230822071959.35620-7-philmd@linaro.org>
2023-08-24target/loongarch: Add avail_FP/FP_SP/FP_DP to check fpu instructionsSong Gao
Signed-off-by: Song Gao <gaosong@loongson.cn> Acked-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20230822032724.1353391-12-gaosong@loongson.cn> Message-Id: <20230822071959.35620-6-philmd@linaro.org>
2023-08-24target/loongarch: Add LoongArch32 cpu la132Jiajie Chen
Add LoongArch32 cpu la132. Due to lack of public documentation of la132, it is currently a synthetic LoongArch32 cpu model. Details need to be added in the future. Signed-off-by: Jiajie Chen <c@jia.je> Signed-off-by: Song Gao <gaosong@loongson.cn> Acked-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20230822032724.1353391-10-gaosong@loongson.cn> Message-Id: <20230822071959.35620-4-philmd@linaro.org>
2023-08-24target/loongarch: Add avail_64 to check la64-only instructionsSong Gao
The la32 instructions listed in Table 2 at https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html#overview-of-basic-integer-instructions Co-authored-by: Jiajie Chen <c@jia.je> Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20230822032724.1353391-9-gaosong@loongson.cn> Message-Id: <20230822071959.35620-3-philmd@linaro.org>
2023-08-24target/loongarch: Add a check parameter to the TRANS macroSong Gao
The default check parmeter is ALL. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20230822032724.1353391-8-gaosong@loongson.cn> Message-Id: <20230822071959.35620-2-philmd@linaro.org>
2023-08-24target/loongarch: Sign extend results in VA32 modeJiajie Chen
In VA32 mode, BL, JIRL and PC* instructions should sign-extend the low 32 bit result to 64 bits. Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20230822032724.1353391-7-gaosong@loongson.cn> Message-Id: <20230822071959.35620-1-philmd@linaro.org>
2023-08-24target/loongarch: Truncate high 32 bits of address in VA32 modeJiajie Chen
When running in VA32 mode(!LA64 or VA32L[1-3] matching PLV), virtual address is truncated to 32 bits before address mapping. Signed-off-by: Jiajie Chen <c@jia.je> Co-authored-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20230822032724.1353391-6-gaosong@loongson.cn> Message-Id: <20230822071405.35386-10-philmd@linaro.org>
2023-08-24target/loongarch: Extract set_pc() helperJiajie Chen
Signed-off-by: Jiajie Chen <c@jia.je> Co-authored-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20230822032724.1353391-6-gaosong@loongson.cn> [PMD: Extract helper from bigger patch] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230822071405.35386-9-philmd@linaro.org>
2023-08-24target/loongarch: Extract make_address_pc() helperJiajie Chen
Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20230822032724.1353391-7-gaosong@loongson.cn> [PMD: Extract helper from bigger patch] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230822071405.35386-8-philmd@linaro.org>
2023-08-24target/loongarch: Extract make_address_i() helperJiajie Chen
Signed-off-by: Jiajie Chen <c@jia.je> Co-authored-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20230822032724.1353391-6-gaosong@loongson.cn> [PMD: Extract helper from bigger patch] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230822071405.35386-7-philmd@linaro.org>
2023-08-24target/loongarch: Extract make_address_x() helperJiajie Chen
Signed-off-by: Jiajie Chen <c@jia.je> Co-authored-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20230822032724.1353391-6-gaosong@loongson.cn> [PMD: Extract helper from bigger patch] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230822071405.35386-6-philmd@linaro.org>
2023-08-24target/loongarch: Add LA64 & VA32 to DisasContextJiajie Chen
Add LA64 and VA32(32-bit Virtual Address) to DisasContext to allow the translator to reject doubleword instructions in LA32 mode for example. Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-ID: <20230822032724.1353391-5-gaosong@loongson.cn> Message-Id: <20230822071405.35386-5-philmd@linaro.org>
2023-08-24target/loongarch: Support LoongArch32 VPPNJiajie Chen
VPPN of TLBEHI/TLBREHI is limited to 19 bits in LA32. Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-ID: <20230822032724.1353391-4-gaosong@loongson.cn> Message-Id: <20230822071405.35386-4-philmd@linaro.org>
2023-08-24target/loongarch: Support LoongArch32 DMWJiajie Chen
LA32 uses a different encoding for CSR.DMW and a new direct mapping mechanism. Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-ID: <20230822032724.1353391-3-gaosong@loongson.cn> Message-Id: <20230822071405.35386-3-philmd@linaro.org>
2023-08-24target/loongarch: Support LoongArch32 TLB entryJiajie Chen
The TLB entry of LA32 lacks NR, NX and RPLV and they are hardwired to zero in LoongArch32. Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-ID: <20230822032724.1353391-2-gaosong@loongson.cn> Message-Id: <20230822071405.35386-2-philmd@linaro.org>
2023-08-24target/loongarch: Add GDB support for loongarch32 modeJiajie Chen
GPRs and PC are 32-bit wide in loongarch32 mode. Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-ID: <20230817093121.1053890-4-gaosong@loongson.cn> [PMD: Rebased, set gdb_num_core_regs] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230821125959.28666-9-philmd@linaro.org>
2023-08-24target/loongarch: Add new object class for loongarch32 cpusJiajie Chen
Add object class stub for future loongarch32 cpus. Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-ID: <20230817093121.1053890-3-gaosong@loongson.cn> [Rebased on TYPE_LOONGARCH64_CPU introduction] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230821125959.28666-8-philmd@linaro.org>
2023-08-24target/loongarch: Add function to check current archJiajie Chen
Add is_la64 function to check if the current cpucfg[1].arch equals to 2(LA64). Signed-off-by: Jiajie Chen <c@jia.je> Co-authored-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Message-ID: <20230817093121.1053890-2-gaosong@loongson.cn> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230821125959.28666-7-philmd@linaro.org>
2023-08-24target/loongarch: Extract 64-bit specifics to loongarch64_cpu_class_initPhilippe Mathieu-Daudé
Extract loongarch64 specific code from loongarch_cpu_class_init() to a new loongarch64_cpu_class_init(). In preparation of supporting loongarch32 cores, rename these functions using the '64' suffix. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230821125959.28666-6-philmd@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn>
2023-08-24target/loongarch: Introduce abstract TYPE_LOONGARCH64_CPUPhilippe Mathieu-Daudé
In preparation of introducing TYPE_LOONGARCH32_CPU, introduce an abstract TYPE_LOONGARCH64_CPU. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230821125959.28666-5-philmd@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn>
2023-08-24target/loongarch: Fix loongarch_la464_initfn() misses setting LSPWSong Gao
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20230817093121.1053890-11-gaosong@loongson.cn> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230821125959.28666-4-philmd@linaro.org>
2023-08-24target/loongarch: Remove duplicated disas_set_info assignmentPhilippe Mathieu-Daudé
Commit 228021f05e ("target/loongarch: Add core definition") sets disas_set_info to loongarch_cpu_disas_set_info. Probably due to a failed git-rebase, commit ca61e75071 ("target/loongarch: Add gdb support") also sets it to the same value. Remove the duplication. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230821125959.28666-3-philmd@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn>
2023-08-24target/loongarch: Log I/O write accesses to CSR registersPhilippe Mathieu-Daudé
Various CSR registers have Read/Write fields. We might want to see guest trying to change such registers. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Song Gao <gaosong@loongson.cn> Message-Id: <20230821125959.28666-2-philmd@linaro.org> Signed-off-by: Song Gao <gaosong@loongson.cn>
2023-07-25other architectures: spelling fixesMichael Tokarev
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2023-07-24target/loongarch: Fix the CSRRD CPUID instruction on big endian hostsThomas Huth
The test in tests/avocado/machine_loongarch.py is currently failing on big endian hosts like s390x. By comparing the traces between running the QEMU_EFI.fd bios on a s390x and on a x86 host, it's quickly obvious that the CSRRD instruction for the CPUID is behaving differently. And indeed: The code currently does a long read (i.e. 64 bit) from the address that points to the CPUState->cpu_index field (with tcg_gen_ld_tl() in the trans_csrrd() function). But this cpu_index field is only an "int" (i.e. 32 bit). While this dirty pointer magic works on little endian hosts, it of course fails on big endian hosts. Fix it by using a proper helper function instead. Message-Id: <20230720175307.854460-1-thuth@redhat.com> Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Thomas Huth <thuth@redhat.com>
generated by cgit v1.2.3 (git 2.26.2) at 2025-03-17 00:25:00 +0000