Age | Commit message (Expand) | Author |
2023-05-18 | target/i386: Fix exception classes for MOVNTPS/MOVNTPD. | Ricky Zhou |
2023-05-18 | target/i386: Fix exception classes for SSE/AVX instructions. | Ricky Zhou |
2023-05-18 | target/i386: Fix and add some comments next to SSE/AVX instructions. | Ricky Zhou |
2023-05-18 | target/i386: fix avx2 instructions vzeroall and vpermdq | Xinyu Li |
2023-05-18 | target/i386: fix operand size for VCOMI/VUCOMI instructions | Paolo Bonzini |
2023-04-23 | tcg: Replace tcg_abort with g_assert_not_reached | Richard Henderson |
2023-04-20 | target/i386: Avoid unreachable variable declaration in mmu_translate() | Peter Maydell |
2023-03-13 | target/i386: Avoid use of tcg_const_* throughout | Richard Henderson |
2023-03-05 | target/i386: Simplify POPF | Richard Henderson |
2023-03-05 | target/i386: Drop tcg_temp_free | Richard Henderson |
2023-03-01 | target/i386: Don't use tcg_temp_local_new | Richard Henderson |
2023-03-01 | accel/tcg: Pass max_insn to gen_intermediate_code by pointer | Richard Henderson |
2023-03-01 | target/i386: Replace `tb_pc()` with `tb->pc` | Anton Johansson |
2023-03-01 | target/i386: Replace `TARGET_TB_PCREL` with `CF_PCREL` | Anton Johansson |
2023-02-28 | accel/tcg: Add 'size' param to probe_access_full | Richard Henderson |
2023-02-27 | target/i386: Fix BZHI instruction | Richard Henderson |
2023-02-16 | target/i386: Fix 32-bit AD[CO]X insns in 64-bit mode | Richard Henderson |
2023-02-11 | target/i386: fix ADOX followed by ADCX | Paolo Bonzini |
2023-02-11 | target/i386: Fix C flag for BLSI, BLSMSK, BLSR | Richard Henderson |
2023-02-11 | target/i386: Fix BEXTR instruction | Richard Henderson |
2023-02-04 | target/i386: Inline cmpxchg16b | Richard Henderson |
2023-02-04 | target/i386: Inline cmpxchg8b | Richard Henderson |
2023-02-04 | target/i386: Split out gen_cmpxchg8b, gen_cmpxchg16b | Richard Henderson |
2023-01-11 | target/i386: fix operand size of unary SSE operations | Paolo Bonzini |
2023-01-11 | i386: Emit correct error code for 64-bit IDT entry | Joe Richey |
2022-12-01 | target/i386: Always completely initialize TranslateFault | Richard Henderson |
2022-12-01 | target/i386: allow MMX instructions with CR4.OSFXSR=0 | Paolo Bonzini |
2022-11-15 | target/i386: hardcode R_EAX as destination register for LAHF/SAHF | Paolo Bonzini |
2022-11-15 | target/i386: fix cmpxchg with 32-bit register destination | Paolo Bonzini |
2022-11-03 | Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging | Stefan Hajnoczi |
2022-11-02 | target/i386: Fix test for paging enabled | Richard Henderson |
2022-11-01 | target/i386: Expand eflags updates inline | Richard Henderson |
2022-11-01 | accel/tcg: Remove will_exit argument from cpu_restore_state | Richard Henderson |
2022-10-31 | target/i386: Fix calculation of LOCK NEG eflags | Qi Hu |
2022-10-26 | target/i386: Convert to tcg_ops restore_state_to_opc | Richard Henderson |
2022-10-22 | target/i386: implement FMA instructions | Paolo Bonzini |
2022-10-20 | target/i386: implement F16C instructions | Paolo Bonzini |
2022-10-20 | target/i386: introduce function to set rounding mode from FPCW or MXCSR bits | Paolo Bonzini |
2022-10-20 | target/i386: decode-new: avoid out-of-bounds access to xmm_regs[-1] | Paolo Bonzini |
2022-10-18 | target/i386: remove old SSE decoder | Paolo Bonzini |
2022-10-18 | target/i386: move 3DNow to the new decoder | Paolo Bonzini |
2022-10-18 | target/i386: implement VLDMXCSR/VSTMXCSR | Paolo Bonzini |
2022-10-18 | target/i386: implement XSAVE and XRSTOR of AVX registers | Paolo Bonzini |
2022-10-18 | target/i386: reimplement 0x0f 0x28-0x2f, add AVX | Paolo Bonzini |
2022-10-18 | target/i386: reimplement 0x0f 0x10-0x17, add AVX | Paolo Bonzini |
2022-10-18 | target/i386: reimplement 0x0f 0xc2, 0xc4-0xc6, add AVX | Paolo Bonzini |
2022-10-18 | target/i386: reimplement 0x0f 0x38, add AVX | Paolo Bonzini |
2022-10-18 | target/i386: Use tcg gvec ops for pmovmskb | Richard Henderson |
2022-10-18 | target/i386: reimplement 0x0f 0x3a, add AVX | Paolo Bonzini |
2022-10-18 | target/i386: reimplement 0x0f 0xd0-0xd7, 0xe0-0xe7, 0xf0-0xf7, add AVX | Paolo Bonzini |