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2021-07-21accel/tcg: Remove TranslatorOps.breakpoint_checkRichard Henderson
The hook is now unused, with breakpoints checked outside translation. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-13target/i386: Correct implementation for FCS, FIP, FDS and FDPZiqiao Kong
Update FCS:FIP and FDS:FDP according to the Intel Manual Vol.1 8.1.8. Note that CPUID.(EAX=07H,ECX=0H):EBX[bit 13] is not implemented by design in this patch and will be added along with TCG features flag in a separate patch later. Signed-off-by: Ziqiao Kong <ziqiaokong@gmail.com> Message-Id: <20210530150112.74411-2-ziqiaokong@gmail.com> [rth: Push FDS/FDP handling down into mod != 3 case; free last_addr.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-13target/i386: Trivial code motion and code style fixZiqiao Kong
A new pair of braces has to be added to declare variables in the case block. The code style is also fixed according to the transalte.c itself during the code motion. Signed-off-by: Ziqiao Kong <ziqiaokong@gmail.com> Message-Id: <20210530150112.74411-1-ziqiaokong@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-12Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210710' ↵Peter Maydell
into staging Add translator_use_goto_tb. Cleanups in prep of breakpoint fixes. Misc fixes. # gpg: Signature made Sat 10 Jul 2021 16:29:14 BST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth-gitlab/tags/pull-tcg-20210710: (41 commits) cpu: Add breakpoint tracepoints tcg: Remove TCG_TARGET_HAS_goto_ptr accel/tcg: Log tb->cflags with -d exec accel/tcg: Split out log_cpu_exec accel/tcg: Move tb_lookup to cpu-exec.c accel/tcg: Move helper_lookup_tb_ptr to cpu-exec.c target/i386: Use cpu_breakpoint_test in breakpoint_handler tcg: Fix prologue disassembly target/xtensa: Use translator_use_goto_tb target/tricore: Use tcg_gen_lookup_and_goto_ptr target/tricore: Use translator_use_goto_tb target/sparc: Use translator_use_goto_tb target/sh4: Use translator_use_goto_tb target/s390x: Remove use_exit_tb target/s390x: Use translator_use_goto_tb target/rx: Use translator_use_goto_tb target/riscv: Use translator_use_goto_tb target/ppc: Use translator_use_goto_tb target/openrisc: Use translator_use_goto_tb target/nios2: Use translator_use_goto_tb ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-07-09target/i386: Use translator_use_goto_tbRichard Henderson
Just use translator_use_goto_tb directly at the one call site, rather than maintaining a local wrapper. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-09tcg: Avoid including 'trace-tcg.h' in target translate.cPhilippe Mathieu-Daudé
The root trace-events only declares a single TCG event: $ git grep -w tcg trace-events trace-events:115:# tcg/tcg-op.c trace-events:137:vcpu tcg guest_mem_before(TCGv vaddr, uint16_t info) "info=%d", "vaddr=0x%016"PRIx64" info=%d" and only a tcg/tcg-op.c uses it: $ git grep -l trace_guest_mem_before_tcg tcg/tcg-op.c therefore it is pointless to include "trace-tcg.h" in each target (because it is not used). Remove it. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210629050935.2570721-1-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-07-09target/i386: fix exceptions for MOV to DRPaolo Bonzini
Use raise_exception_ra (without error code) when raising the illegal opcode operation; raise #GP when setting bits 63:32 of DR6 or DR7. Move helper_get_dr to sysemu/ since it is a privileged instruction that is not needed on user-mode emulators. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-06-29target/i386: Improve bswap translationRichard Henderson
Use a break instead of an ifdefed else. There's no need to move the values through s->T0. Remove TCG_BSWAP_IZ and the preceding zero-extension. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-29tcg: Add flags argument to tcg_gen_bswap16_*, tcg_gen_bswap32_i64Richard Henderson
Implement the new semantics in the fallback expansion. Change all callers to supply the flags that keep the semantics unchanged locally. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-06-04target/i386: Fix decode of cr8Richard Henderson
A recent cleanup did not recognize that there are two ways to encode cr8: one via the LOCK and the other via REX. Fixes: 7eff2e7c Resolves: https://gitlab.com/qemu-project/qemu/-/issues/380 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210602035511.96834-1-richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2021-05-20Merge remote-tracking branch 'remotes/cohuck-gitlab/tags/s390x-20210520-v2' ↵Peter Maydell
into staging s390x fixes and cleanups; also related fixes in xtensa, arm, and x86 code # gpg: Signature made Thu 20 May 2021 13:23:15 BST # gpg: using RSA key C3D0D66DC3624FF6A8C018CEDECF6B93C6F02FAF # gpg: issuer "cohuck@redhat.com" # gpg: Good signature from "Cornelia Huck <conny@cornelia-huck.de>" [unknown] # gpg: aka "Cornelia Huck <huckc@linux.vnet.ibm.com>" [full] # gpg: aka "Cornelia Huck <cornelia.huck@de.ibm.com>" [full] # gpg: aka "Cornelia Huck <cohuck@kernel.org>" [unknown] # gpg: aka "Cornelia Huck <cohuck@redhat.com>" [unknown] # Primary key fingerprint: C3D0 D66D C362 4FF6 A8C0 18CE DECF 6B93 C6F0 2FAF * remotes/cohuck-gitlab/tags/s390x-20210520-v2: tests/tcg/x86_64: add vsyscall smoke test target/i386: Make sure that vsyscall's tb->size != 0 vfio-ccw: Attempt to clean up all IRQs on error hw/s390x/ccw: Register qbus type in abstract TYPE_CCW_DEVICE parent vfio-ccw: Permit missing IRQs accel/tcg: Assert that tb->size != 0 after translation target/xtensa: Make sure that tb->size != 0 target/arm: Make sure that commpage's tb->size != 0 target/s390x: Fix translation exception on illegal instruction Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-05-20target/i386: Make sure that vsyscall's tb->size != 0Ilya Leoshkevich
tb_gen_code() assumes that tb->size must never be zero, otherwise it may produce spurious exceptions. For x86_64 this may happen when creating a translation block for the vsyscall page. Fix by pretending that vsyscall translation blocks have at least one instruction. Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210519045738.1335210-2-iii@linux.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-05-19target/i386: Remove user-only i/o stubsRichard Henderson
With the previous patch for check_io, we now have enough for the compiler to dead-code eliminate all of the i/o helpers. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210514151342.384376-51-richard.henderson@linaro.org>
2021-05-19target/i386: Move helper_check_io to sysemuRichard Henderson
The we never allow i/o from user-only, and the tss check that helper_check_io does will always fail. Use an ifdef within gen_check_io and return false, indicating that an exception is known to be raised. Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210514151342.384376-50-richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-19target/i386: Create helper_check_ioRichard Henderson
Drop helper_check_io[bwl] and expose their common subroutine to tcg directly. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210514151342.384376-49-richard.henderson@linaro.org>
2021-05-19target/i386: Pass in port to gen_check_ioRichard Henderson
Pass in a pre-truncated TCGv_i32 value. We were doing the truncation of EDX in multiple places, now only once per insn. While all callers use s->tmp2_i32, for cleanliness of the subroutine, use a parameter anyway. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210514151342.384376-48-richard.henderson@linaro.org>
2021-05-19target/i386: Tidy gen_check_ioRichard Henderson
Get cur_eip from DisasContext. Do not require the caller to use svm_is_rep; get prefix from DisasContext. Use the proper symbolic constants for SVM_IOIO_*. While we're touching all call sites, return bool in preparation for gen_check_io raising #GP. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210514151342.384376-47-richard.henderson@linaro.org>
2021-05-19target/i386: Exit tb after wrmsrRichard Henderson
At minimum, wrmsr can change efer, which affects HF_LMA. Cc: qemu-stable@nongnu.org Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210514151342.384376-46-richard.henderson@linaro.org>
2021-05-19target/i386: Eliminate user stubs for read/write_crN, rd/wrmsrRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210514151342.384376-45-richard.henderson@linaro.org>
2021-05-19target/i386: Unify invlpg, invlpgaRichard Henderson
Use a single helper, flush_page, to do the work. Use gen_svm_check_intercept. Perform the zero-extension for invlpga inline. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210514151342.384376-43-richard.henderson@linaro.org>
2021-05-19target/i386: Move invlpg, hlt, monitor, mwait to sysemuRichard Henderson
These instructions are all privileged. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210514151342.384376-42-richard.henderson@linaro.org>
2021-05-19target/i386: Cleanup read_crN, write_crN, lmswRichard Henderson
Pull the svm intercept check into the translator. Pull the entire implementation of lmsw into the translator. Push the check for CR8LEG into the regno validation switch. Unify the gen_io_start check between read/write. Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210514151342.384376-40-richard.henderson@linaro.org>
2021-05-19target/i386: Remove pc_start argument to gen_svm_check_interceptRichard Henderson
When exiting helper_svm_check_intercept via exception, cpu_vmexit calls cpu_restore_state, which will recover eip and cc_op via unwind. Therefore we do not need to store eip or cc_op before the call. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210514151342.384376-38-richard.henderson@linaro.org>
2021-05-19target/i386: Tidy svm_check_intercept from tcgRichard Henderson
The param argument to helper_svm_check_intercept_param is always 0; eliminate it and rename to helper_svm_check_intercept. Fold gen_svm_check_intercept_param into gen_svm_check_intercept. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210514151342.384376-37-richard.henderson@linaro.org>
2021-05-19target/i386: Simplify gen_debug usageRichard Henderson
Both invocations pass the start of the current instruction, which is available as s->base.pc_next. The function sets is_jmp, so we can eliminate a second setting. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210514151342.384376-36-richard.henderson@linaro.org>
2021-05-19target/i386: Mark some helpers as noreturnRichard Henderson
Any helper that always raises an exception or interrupt, or simply exits to the main loop, can be so marked. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210514151342.384376-35-richard.henderson@linaro.org>
2021-05-19target/i386: Eliminate SVM helpers for user-onlyRichard Henderson
Use STUB_HELPER to ensure that such calls are always eliminated. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210514151342.384376-34-richard.henderson@linaro.org>
2021-05-19target/i386: Implement skinit in translate.cRichard Henderson
Our sysemu implementation is a stub. We can already intercept instructions for vmexit, and raising #UD is trivial. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210514151342.384376-33-richard.henderson@linaro.org>
2021-05-19target/i386: Assert !GUEST for user-onlyRichard Henderson
For user-only, we do not need to check for VMM intercept. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210514151342.384376-32-richard.henderson@linaro.org>
2021-05-19target/i386: Assert !SVME for user-onlyRichard Henderson
Most of the VMM instructions are already disabled for user-only, by being usable only from ring 0. The spec is intentionally loose for VMMCALL, allowing the VMM to define syscalls for user-only. However, we're not emulating any VMM, so VMMCALL can just raise #UD unconditionally. Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210514151342.384376-31-richard.henderson@linaro.org>
2021-05-19target/i386: Add stub generator for helper_set_drRichard Henderson
This removes an ifdef from the middle of disas_insn, and ensures that the branch is not reachable. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210514151342.384376-30-richard.henderson@linaro.org>
2021-05-19target/i386: Reorder DisasContext membersRichard Henderson
Sort all of the single-byte members to the same area of the structure, eliminating 8 bytes of padding. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210514151342.384376-29-richard.henderson@linaro.org>
2021-05-19target/i386: Fix the comment for repz_optRichard Henderson
After fixing a typo in the comment, fixup for CODING_STYLE. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210514151342.384376-28-richard.henderson@linaro.org>
2021-05-19target/i386: Reduce DisasContext jmp_opt, repz_opt to boolRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210514151342.384376-27-richard.henderson@linaro.org>
2021-05-19target/i386: Leave TF in DisasContext.flagsRichard Henderson
It's just as easy to clear the flag with AND than assignment. In two cases the test for the bit can be folded together with the test for HF_INHIBIT_IRQ_MASK. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210514151342.384376-26-richard.henderson@linaro.org>
2021-05-19target/i386: Reduce DisasContext popl_esp_hack and rip_offset to uint8_tRichard Henderson
Both of these fields store the size of a single memory access, so the range of values is 0-8. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210514151342.384376-25-richard.henderson@linaro.org>
2021-05-19target/i386: Reduce DisasContext.vex_[lv] to uint8_tRichard Henderson
Currently, vex_l is either {0,1}; if in the future we implement AVX-512, the max value will be 2. In vex_v we store a register number. This is 0-15 for SSE, and 0-31 for AVX-512. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210514151342.384376-24-richard.henderson@linaro.org>
2021-05-19target/i386: Reduce DisasContext.prefix to uint8_tRichard Henderson
The highest bit in this set is 0x40 (PREFIX_REX). Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210514151342.384376-23-richard.henderson@linaro.org>
2021-05-19target/i386: Reduce DisasContext.override to int8_tRichard Henderson
The range of values is -1 (none) to 5 (R_GS). Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210514151342.384376-22-richard.henderson@linaro.org>
2021-05-19target/i386: Reduce DisasContext.flags to uint32_tRichard Henderson
The value comes from tb->flags, which is uint32_t. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210514151342.384376-21-richard.henderson@linaro.org>
2021-05-19target/i386: Remove DisasContext.f_st as unusedRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210514151342.384376-20-richard.henderson@linaro.org>
2021-05-19target/i386: Move rex_w into DisasContextRichard Henderson
Treat this flag exactly like we treat the other rex bits. The -1 initialization is unused; the two tests are > 0 and == 1, so the value can be reduced to a bool. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210514151342.384376-19-richard.henderson@linaro.org>
2021-05-19target/i386: Move rex_r into DisasContextRichard Henderson
Treat this flag exactly like we treat rex_b and rex_x. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210514151342.384376-18-richard.henderson@linaro.org>
2021-05-19target/i386: Tidy REX_B, REX_X definitionRichard Henderson
Change the storage from int to uint8_t since the value is in {0,8}. For x86_64 add 0 in the macros to (1) promote the type back to int, and (2) make the macro an rvalue. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210514151342.384376-17-richard.henderson@linaro.org>
2021-05-19target/i386: Introduce REX_PREFIXRichard Henderson
The existing flag, x86_64_hregs, does not accurately describe its setting. It is true if and only if a REX prefix has been seen. Yes, that affects the "h" regs, but that's secondary. Add PREFIX_REX and include this bit in s->prefix. Add REX_PREFIX so that the check folds away when x86_64 is compiled out. Fold away the reg >= 8 check, because bit 3 of the register number comes from the REX prefix in the first place. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210514151342.384376-16-richard.henderson@linaro.org>
2021-05-19target/i386: Assert !ADDSEG for x86_64 user-onlyRichard Henderson
LMA disables traditional segmentation, exposing a flat address space. This means that ADDSEG is off. Since we're adding an accessor macro, pull the value directly out of flags otherwise. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210514151342.384376-15-richard.henderson@linaro.org>
2021-05-19target/i386: Assert LMA for x86_64 user-onlyRichard Henderson
LMA is a pre-requisite for CODE64, so there is no way to disable it for x86_64-linux-user, and there is no way to enable it for i386. Since we're adding an accessor macro, pull the value directly out of flags when we're not assuming a constant. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210514151342.384376-14-richard.henderson@linaro.org>
2021-05-19target/i386: Assert CODE64 for x86_64 user-onlyRichard Henderson
For x86_64 user-only, there is no way to leave 64-bit mode. Without x86_64, there is no way to enter 64-bit mode. There is an existing macro to aid with that; simply place it in the right place in the ifdef chain. Since we're adding an accessor macro, pull the value directly out of flags when we're not assuming a constant. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210514151342.384376-13-richard.henderson@linaro.org>
2021-05-19target/i386: Assert SS32 for x86_64 user-onlyRichard Henderson
For user-only, SS32 == !VM86, because we are never in real-mode. Since we cannot enter vm86 mode for x86_64 user-only, SS32 is always set. Since we're adding an accessor macro, pull the value directly out of flags otherwise. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210514151342.384376-12-richard.henderson@linaro.org>
2021-05-19target/i386: Assert CODE32 for x86_64 user-onlyRichard Henderson
For user-only, CODE32 == !VM86, because we are never in real-mode. Since we cannot enter vm86 mode for x86_64 user-only, CODE32 is always set. Since we're adding an accessor macro, pull the value directly out of flags otherwise. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210514151342.384376-11-richard.henderson@linaro.org>
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