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2023-11-20Merge tag 'hppa64-fixes-pull-request' of ↵Stefan Hajnoczi
https://github.com/hdeller/qemu-hppa into staging HPPA64-PATCHES-for-8.2 Two patches for 8.2. The SHRPD patch fixes a real translation bug which then allows to boot the 64-bit Linux kernels of the Debian-11 and Debian-12 installation CDs. The second patch adds the instruction byte sequence to the assembly log. This is not an actual bug fix, but it's important since it helps a lot when trying to fix qemu translation bugs on hppa. # -----BEGIN PGP SIGNATURE----- # # iHUEABYKAB0WIQS86RI+GtKfB8BJu973ErUQojoPXwUCZVfHPwAKCRD3ErUQojoP # X3TrAQD2SfFsTWIYqTamh1ZHmydaJRL1xhXmPMqXgXFkDmiyhQD/VeyIyWEGj5Oe # x70WR8HrtkadsUddgSGzFRChaVb0/wI= # =Sapq # -----END PGP SIGNATURE----- # gpg: Signature made Fri 17 Nov 2023 15:04:15 EST # gpg: using EDDSA key BCE9123E1AD29F07C049BBDEF712B510A23A0F5F # gpg: Good signature from "Helge Deller <deller@gmx.de>" [unknown] # gpg: aka "Helge Deller <deller@kernel.org>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 4544 8228 2CD9 10DB EF3D 25F8 3E5F 3D04 A7A2 4603 # Subkey fingerprint: BCE9 123E 1AD2 9F07 C049 BBDE F712 B510 A23A 0F5F * tag 'hppa64-fixes-pull-request' of https://github.com/hdeller/qemu-hppa: disas/hppa: Show hexcode of instruction along with disassembly target/hppa: Fix 64-bit SHRPD instruction Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2023-11-17target/hppa: Fix 64-bit SHRPD instructionHelge Deller
When shifting the two joined 64-bit registers right, shift the upper 64-bit register to the left and the lower 64-bit register to the right before merging them with OR. Signed-off-by: Helge Deller <deller@gmx.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-15target/hppa: spelling fixes: Indicies, TruelyMichael Tokarev
Fixes: bb67ec32a0bb "target/hppa: Include PSW_P in tb flags and mmu index" Fixes: d7553f3591bb "target/hppa: Populate an interval tree with valid tlb entries" Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2023-11-13target/hppa: Reduce TARGET_PHYS_ADDR_SPACE_BITS to 40Richard Henderson
This is the value that is supported by both PA-8500 and Astro. If we support a larger address space than expected, we trip up software that did not fill in all of the page table bits, expecting them to be ignored. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-13target/hppa: Replace MMU_PHYS_IDX with MMU_ABS_IDX, MMU_ABS_W_IDXRichard Henderson
Align the language with pa2.0, separating absolute and physical. The translation from absolute to physical depends on PSW.W, and we prefer not to flush between changes, therefore use 2 mmu_idx. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-13target/hppa: Introduce MMU_IDX_MMU_DISABLEDRichard Henderson
Reduce the number of direct checks against MMU_PHYS_IDX. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-13target/hppa: Fix possible overflow in TLB size calculationHelge Deller
Coverty found that the shift of TARGET_PAGE_SIZE (32-bit type) might overflow. Fix it by casting TARGET_PAGE_SIZE to a 64-bit type before doing the shift (CID 1523902 and CID 1523908). Reported-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Helge Deller <deller@gmx.de> Message-Id: <ZU6F/H8CZr3q4pP/@p100> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-13target/hppa: Fix calculation of CR_IIASQ back registerHelge Deller
Need to use iasq_b and iaoq_b to determine back register of CR_IIASQ. This fixes random faults when booting up Linux user space. Signed-off-by: Helge Deller <deller@gmx.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-13target/hppa: Use PRIV_P_TO_MMU_IDX in helper_probeRichard Henderson
Direct privilege level to mmu_idx mapping has been false for some time. Provide the correct value to hppa_get_physical_address. Fixes: fa824d99f9b ("target/hppa: Switch to use MMU indices 11-15") Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-13target/hppa: Use only low 2 immediate bits for PROBEIRichard Henderson
During the conversion to decodetree, the 2-bit mask was lost. Fixes: deee69a19fd ("target/hppa: Convert memory management insns") Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-12target/hppa: Mask reserved PSW bits in expand_sm_immHelge Deller
The system mask is a restricted subset of the psw, with only a couple of reserved bits. It is better to handle this up front in the translator than require helper_swap_system_mask to use cpu_hppa_get_psw and cpu_hppa_put_psw. Signed-off-by: Helge Deller <deller@gmx.de> [rth: Handle this in expand_sm_imm not helper_swap_system_mask.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-07target: Move ArchCPUClass definition to 'cpu.h'Philippe Mathieu-Daudé
The OBJECT_DECLARE_CPU_TYPE() macro forward-declares each ArchCPUClass type. These forward declarations are sufficient for code in hw/ to use the QOM definitions. No need to expose these structure definitions. Keep each local to their target/ by moving them to the corresponding "cpu.h" header. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231013140116.255-13-philmd@linaro.org>
2023-11-07target: Mention 'cpu-qom.h' is target agnosticPhilippe Mathieu-Daudé
"target/foo/cpu-qom.h" is supposed to be target agnostic (include-able by any target). Add such mention in the header. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20231013140116.255-3-philmd@linaro.org>
2023-11-07target: Unify QOM stylePhilippe Mathieu-Daudé
Enforce the style described by commit 067109a11c ("docs/devel: mention the spacing requirement for QOM"): The first declaration of a storage or class structure should always be the parent and leave a visual space between that declaration and the new code. It is also useful to separate backing for properties (options driven by the user) and internal state to make navigation easier. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20231013140116.255-2-philmd@linaro.org>
2023-11-06target/hppa: Improve interrupt loggingRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Update IIAOQ, IIASQ for pa2.0Richard Henderson
These registers have a different format for pa2.0. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Create raise_exception_with_iorRichard Henderson
Handle pa2.0 logic for filling in ISR+IOR. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Add unwind_breg to CPUHPPAStateRichard Henderson
Fill in the insn_start value during form_gva, and copy it out to the env field in hppa_restore_state_to_opc. The value is not yet consumed. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Clear upper bits in mtctl for pa1.xHelge Deller
Signed-off-by: Helge Deller <deller@gmx.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Avoid async_safe_run_on_cpu on uniprocessor systemRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Add pa2.0 cpu local tlb flushesHelge Deller
The previous decoding misnamed the bit it called "local". Other than the name, the implementation was correct for pa1.x. Rename this field to "tlbe". PA2.0 adds (a real) local bit to PxTLB, and also adds a range of pages to flush in GR[b]. Signed-off-by: Helge Deller <deller@gmx.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement pa2.0 data prefetch instructionsRichard Henderson
These are aliased onto the normal integer loads to %g0. Since we don't emulate caches, prefetch is a nop. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Return zero for r0 from load_gprRichard Henderson
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Precompute zero into DisasContextRichard Henderson
Reduce the number of times we look for the constant 0. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Fix interruption based on default PSWHelge Deller
The default PSW is set by the operating system with the PDC_PSW firmware call. Use that setting to decide if wide mode is to be enabled for interruptions and EIRR usage. Signed-off-by: Helge Deller <deller@gmx.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement PERMHRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement MIXH, MIXWRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement HSHLADD, HSHRADDRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement HSHL, HSHRRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement HAVGRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement HSUBRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement HADDRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Replace tcg_gen_*_tl with tcg_gen_*_i64Richard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Use tcg_temp_new_i64 not tcg_temp_newRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Adjust vmstate_env for pa2.0 tlbRichard Henderson
Split out the tlb to a subsection so that it can be separately versioned -- the format is only partially following the architecture and is partially guided by the qemu implementation. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Remove remaining TARGET_REGISTER_BITS redirectionsRichard Henderson
The conversions to/from i64 can be eliminated entirely, folding computation into adjacent operations. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Remove most of the TARGET_REGISTER_BITS redirectionsRichard Henderson
Remove all but those intended to change type to or from i64. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Remove TARGET_REGISTER_BITSRichard Henderson
Rely only on TARGET_LONG_BITS, fixed at 64, and hppa_is_pa20. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement IDTLBT, IITLBTRichard Henderson
Rename the existing insert tlb helpers to emphasize that they are for pa1.1 cpus. Implement a combined i/d tlb for pa2.0. Still missing is the new 'P' tlb bit. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement STDBYRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement CLRBTS, POPBTS, PUSHBTS, PUSHNOMRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement SHRPDRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement EXTRDRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement DEPD, DEPDIRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Implement LDD, LDCD, LDDA, STD, STDARichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Decode ADDB double-wordRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Decode CMPIB double-wordRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Decode d for cmpb instructionsRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Decode d for bb instructionsRichard Henderson
Manipulate the shift count so that the bit to be tested is always placed at the MSB. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-11-06target/hppa: Decode d for sub instructionsRichard Henderson
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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