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2023-11-28target/hexagon/idef-parser/prepare: use env to invoke bashSamuel Tardieu
This file is the only one involved in the compilation process which still uses the /bin/bash path. Signed-off-by: Samuel Tardieu <sam@rfc1149.net> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Anton Johansson <anjo@rev.ng> Message-ID: <20231123211506.636533-1-sam@rfc1149.net> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-10-03tcg: Rename cpu_env to tcg_envRichard Henderson
Allow the name 'cpu_env' to be used for something else. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-09-08hexagon: spelling fixesMichael Tokarev
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Brian Cain <bcain@quicinc.com>
2023-06-05target/hexagon: Include helper-gen.h where neededRichard Henderson
This had been included via tcg-op-common.h via tcg-op.h, but that is going away. In idef-parser.y, shuffle some tcg related includes into a more logical order. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-05-18target/hexagon: fix = vs. == mishapPaolo Bonzini
**** Changes in v2 **** Fix yyassert's for sign and zero extends Coverity reports a parameter that is "set but never used". This is caused by an assignment operator being used instead of equality. Co-authored-by: Taylor Simpson <tsimpson@quicinc.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Anton Johansson <anjo@rev.ng> Tested-by: Anton Johansson <anjo@rev.ng> Message-Id: <20230428204411.1400931-1-tsimpson@quicinc.com>
2023-05-18Hexagon (target/hexagon) Additional instructions handled by idef-parserTaylor Simpson
**** Changes in v3 **** Fix bugs exposed by dpmpyss_rnd_s0 instruction Set correct size/signedness for constants Test cases added to tests/tcg/hexagon/misc.c **** Changes in v2 **** Fix bug in imm_print identified in clang build Currently, idef-parser skips all floating point instructions. However, there are some floating point instructions that can be handled. The following instructions are now parsed F2_sfimm_p F2_sfimm_n F2_dfimm_p F2_dfimm_n F2_dfmpyll F2_dfmpylh To make these instructions work, we fix some bugs in parser-helpers.c gen_rvalue_extend gen_cast_op imm_print lexer properly sets size/signedness of constants Test cases added to tests/tcg/hexagon/fpstuff.c Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Tested-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Anton Johansson <anjo@rev.ng> Message-Id: <20230501203125.4025991-1-tsimpson@quicinc.com>
2023-05-18Hexagon (target/hexagon) Move new_pred_value to DisasContextTaylor Simpson
The new_pred_value array in the CPUHexagonState is only used for bookkeeping within the translation of a packet. With recent changes that eliminate the need to free TCGv variables, these make more sense to be transient and kept in DisasContext. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230427230012.3800327-19-tsimpson@quicinc.com>
2023-05-18Hexagon (target/hexagon) Add DisasContext arg to gen_log_reg_writeTaylor Simpson
Add DisasContext arg to gen_log_reg_write_pair also Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230427230012.3800327-3-tsimpson@quicinc.com>
2023-05-05target/Hexagon: Finish conversion to tcg_gen_qemu_{ld, st}_*Richard Henderson
Convert away from the old interface with the implicit MemOp argument. Importantly, this removes some incorrect casts generated by idef-parser's gen_load(). Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Anton Johansson <anjo@rev.ng> Message-Id: <20230502135741.1158035-4-richard.henderson@linaro.org>
2023-04-21Hexagon (target/hexagon) Updates to USR should use get_result_gprTaylor Simpson
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Anton Johansson <anjo@rev.ng> Message-Id: <20230405164211.30015-3-tsimpson@quicinc.com>
2023-03-06Hexagon (target/hexagon) Reduce manipulation of slot_cancelledTaylor Simpson
We only need to track slot for predicated stores and predicated HVX instructions. Add arguments to the probe helper functions to indicate if the slot is predicated. Here is a simple example of the differences in the TCG code generated: IN: 0x00400094: 0xf900c102 { if (P0) R2 = and(R0,R1) } BEFORE ---- 00400094 mov_i32 slot_cancelled,$0x0 mov_i32 new_r2,r2 and_i32 tmp0,p0,$0x1 brcond_i32 tmp0,$0x0,eq,$L1 and_i32 tmp0,r0,r1 mov_i32 new_r2,tmp0 br $L2 set_label $L1 or_i32 slot_cancelled,slot_cancelled,$0x8 set_label $L2 mov_i32 r2,new_r2 AFTER ---- 00400094 mov_i32 new_r2,r2 and_i32 tmp0,p0,$0x1 brcond_i32 tmp0,$0x0,eq,$L1 and_i32 tmp0,r0,r1 mov_i32 new_r2,tmp0 br $L2 set_label $L1 set_label $L2 mov_i32 r2,new_r2 Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Anton Johansson <anjo@rev.ng> Message-Id: <20230307025828.1612809-14-tsimpson@quicinc.com>
2023-03-06Hexagon (target/hexagon) Remove gen_log_predicated_reg_write[_pair]Taylor Simpson
We assign the instruction destination register to hex_new_value[num] instead of a TCG temp that gets copied back to hex_new_value[num]. We introduce new functions get_result_gpr[_pair] to facilitate getting the proper destination register. Since we preload hex_new_value for predicated instructions, we don't need the check for slot_cancelled. So, we call gen_log_reg_write instead. We update the helper function generation and gen_tcg.h to maintain the disable-hexagon-idef-parser configuration. Here is a simple example of the differences in the TCG code generated: IN: 0x00400094: 0xf900c102 { if (P0) R2 = and(R0,R1) } BEFORE ---- 00400094 mov_i32 slot_cancelled,$0x0 mov_i32 new_r2,r2 mov_i32 loc2,$0x0 and_i32 tmp0,p0,$0x1 brcond_i32 tmp0,$0x0,eq,$L1 and_i32 tmp0,r0,r1 mov_i32 loc2,tmp0 br $L2 set_label $L1 or_i32 slot_cancelled,slot_cancelled,$0x8 set_label $L2 and_i32 tmp0,slot_cancelled,$0x8 movcond_i32 new_r2,tmp0,$0x0,loc2,new_r2,eq mov_i32 r2,new_r2 AFTER ---- 00400094 mov_i32 slot_cancelled,$0x0 mov_i32 new_r2,r2 and_i32 tmp0,p0,$0x1 brcond_i32 tmp0,$0x0,eq,$L1 and_i32 tmp0,r0,r1 mov_i32 new_r2,tmp0 br $L2 set_label $L1 or_i32 slot_cancelled,slot_cancelled,$0x8 set_label $L2 mov_i32 r2,new_r2 We'll remove the unnecessary manipulation of slot_cancelled in a subsequent patch. Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Anton Johansson <anjo@rev.ng> Message-Id: <20230307025828.1612809-13-tsimpson@quicinc.com>
2023-03-06Hexagon (target/hexagon) Analyze packet before generating TCGTaylor Simpson
We create a new generator that creates an analyze_<tag> function for each instruction. Currently, these functions record the writes to R, P, and C registers by calling ctx_log_reg_write[_pair] or ctx_log_pred_write. During gen_start_packet, we invoke the analyze_<tag> function for each instruction in the packet, and we mark the implicit register and predicate writes. Doing the analysis up front has several advantages - We remove calls to ctx_log_* from gen_tcg_funcs.py and genptr.c - After the analysis is performed, we can initialize hex_new_value for each of the predicated assignments rather than during TCG generation for the instructions - This is a stepping stone for future work where the analysis will include the set of registers that are read. In cases where the packet doesn't have an overlap between the registers that are written and registers that are read, we can avoid the intermediate step of writing to hex_new_value. Note that other checks will also be needed (e.g., no instructions can raise an exception). Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Anton Johansson <anjo@rev.ng> Message-Id: <20230307025828.1612809-6-tsimpson@quicinc.com>
2023-03-06target/hexagon/idef-parser: Remove unused code pathsAnton Johansson
Removes code paths used by COF instructions, which are no longer processed by idef-parser. Tested-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Signed-off-by: Anton Johansson <anjo@rev.ng> Message-Id: <20230131223133.8592-1-anjo@rev.ng>
2023-03-06target/hexagon/idef-parser: Elide mov in gen_pred_assignRichard Henderson
Merge mov with andi. Suggested-by: Taylor Simpson <tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20230306225724.2105263-1-richard.henderson@linaro.org>
2023-03-05target/hexagon/idef-parser: Use gen_constant for gen_extend_tcg_width_opRichard Henderson
We already have a temporary, res, which we can use for the intermediate shift result. Simplify the constant to -1 instead of 0xf*f. This was the last use of gen_tmp_value, so remove it. Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-05target/hexagon/idef-parser: Use gen_tmp for gen_rvalue_predRichard Henderson
The allocation is immediately followed by either tcg_gen_mov_i32 or gen_read_preg (which contains tcg_gen_mov_i32), so the zero initialization is immediately discarded. Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-05target/hexagon/idef-parser: Use gen_tmp for gen_pred_assignRichard Henderson
The allocation is immediately followed by tcg_gen_mov_i32, so the initial assignment of zero is discarded. Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-05target/hexagon/idef-parser: Use gen_tmp for LPCFGRichard Henderson
The GET_USR_FIELD macro initializes the output, so the initial assignment of zero is discarded. This is the only use of get_tmp_value outside of parser-helper.c, so make it static. Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-05target/hexagon: Use tcg_constant_* for gen_constant_from_immRichard Henderson
Rename from gen_tmp_value_from_imm to match gen_constant vs gen_tmp. Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-05target/hexagon/idef-parser: Drop HexValue.is_manualRichard Henderson
This field is no longer used. Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-05target/hexagon/idef-parser: Drop tcg_temp_freeRichard Henderson
Translators are no longer required to free tcg temporaries. This removes gen_rvalue_free, gen_rvalue_free_manual and free_variables, whose only purpose was to emit tcg_temp_free. Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-01target/hexagon/idef-parser: Drop gen_tmp_localRichard Henderson
This is now equivalent to gen_tmp. Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-03-01target/hexagon: Don't use tcg_temp_local_new_*Richard Henderson
Since tcg_temp_new_* is now identical, use those. Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-01-05target/hexagon: suppress unused variable warningAlessandro Di Federico
This patch manually suppresses a warning for an unused variable (yynerrs) emitted by bison. This warning has been triggered for the first time by clang 15. This patch also disables `-Wextra`, which is not usually adopted in QEMU. However, clang 15 triggers the warning fixed in this patch even in absence of `-Wextra`. Signed-off-by: Alessandro Di Federico <ale@rev.ng> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Tested-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20221221155327.1504117-1-ale@rev.ng>
2023-01-05target/hexagon/idef-parser: fix two typos in READMEMatheus Tavares Bernardino
Signed-off-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Alessandro Di Federico <ale@rev.ng> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <fe67371e03f9dde38eb7554937da0a96a230730e.1672174122.git.quic_mathbern@quicinc.com>
2022-12-16target/hexagon: import parser for idef-parserAnton Johansson
Signed-off-by: Alessandro Di Federico <ale@rev.ng> Signed-off-by: Paolo Montesel <babush@rev.ng> Signed-off-by: Anton Johansson <anjo@rev.ng> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20220923173831.227551-10-anjo@rev.ng>
2022-12-16target/hexagon: import lexer for idef-parserPaolo Montesel
Signed-off-by: Alessandro Di Federico <ale@rev.ng> Signed-off-by: Paolo Montesel <babush@rev.ng> Signed-off-by: Anton Johansson <anjo@rev.ng> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20220923173831.227551-9-anjo@rev.ng>
2022-12-16target/hexagon: prepare input for the idef-parserAlessandro Di Federico
Introduce infrastructure necessary to produce a file suitable for being parsed by the idef-parser. A build option is also added to fully disable the output of idef-parser, which is useful for debugging. Signed-off-by: Alessandro Di Federico <ale@rev.ng> Signed-off-by: Anton Johansson <anjo@rev.ng> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20220923173831.227551-8-anjo@rev.ng>
2022-12-16target/hexagon: import README for idef-parserAlessandro Di Federico
Signed-off-by: Alessandro Di Federico <ale@rev.ng> Signed-off-by: Anton Johansson <anjo@rev.ng> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20220923173831.227551-3-anjo@rev.ng>
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