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path: root/target/hexagon/hex_common.py
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2023-03-06Hexagon (target/hexagon) Remove gen_log_predicated_reg_write[_pair]Taylor Simpson
We assign the instruction destination register to hex_new_value[num] instead of a TCG temp that gets copied back to hex_new_value[num]. We introduce new functions get_result_gpr[_pair] to facilitate getting the proper destination register. Since we preload hex_new_value for predicated instructions, we don't need the check for slot_cancelled. So, we call gen_log_reg_write instead. We update the helper function generation and gen_tcg.h to maintain the disable-hexagon-idef-parser configuration. Here is a simple example of the differences in the TCG code generated: IN: 0x00400094: 0xf900c102 { if (P0) R2 = and(R0,R1) } BEFORE ---- 00400094 mov_i32 slot_cancelled,$0x0 mov_i32 new_r2,r2 mov_i32 loc2,$0x0 and_i32 tmp0,p0,$0x1 brcond_i32 tmp0,$0x0,eq,$L1 and_i32 tmp0,r0,r1 mov_i32 loc2,tmp0 br $L2 set_label $L1 or_i32 slot_cancelled,slot_cancelled,$0x8 set_label $L2 and_i32 tmp0,slot_cancelled,$0x8 movcond_i32 new_r2,tmp0,$0x0,loc2,new_r2,eq mov_i32 r2,new_r2 AFTER ---- 00400094 mov_i32 slot_cancelled,$0x0 mov_i32 new_r2,r2 and_i32 tmp0,p0,$0x1 brcond_i32 tmp0,$0x0,eq,$L1 and_i32 tmp0,r0,r1 mov_i32 new_r2,tmp0 br $L2 set_label $L1 or_i32 slot_cancelled,slot_cancelled,$0x8 set_label $L2 mov_i32 r2,new_r2 We'll remove the unnecessary manipulation of slot_cancelled in a subsequent patch. Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Anton Johansson <anjo@rev.ng> Message-Id: <20230307025828.1612809-13-tsimpson@quicinc.com>
2023-03-06Hexagon (target/hexagon) Don't set pkt_has_store_s1 when not neededTaylor Simpson
The pkt_has_store_s1 field in CPUHexagonState is only needed in generated helpers for scalar load instructions. See check_noshuf and mem_load[1248] in op_helper.c. We add logic in gen_analyze_funcs.py to set need_pkt_has_store_s1 in DisasContext when it is needed at runtime. Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Anton Johansson <anjo@rev.ng> Message-Id: <20230307025828.1612809-7-tsimpson@quicinc.com>
2022-12-16target/hexagon: call idef-parser functionsAlessandro Di Federico
Extend gen_tcg_funcs.py in order to emit calls to the functions emitted by the idef-parser, if available. Signed-off-by: Alessandro Di Federico <ale@rev.ng> Signed-off-by: Anton Johansson <anjo@rev.ng> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20220923173831.227551-11-anjo@rev.ng>
2022-12-16Hexagon (target/hexagon) Remove next_PC from runtime stateTaylor Simpson
The imported files don't properly mark all CONDEXEC instructions, so we add some logic to hex_common.py to add the attribute. Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20221108162906.3166-7-tsimpson@quicinc.com>
2022-12-16Hexagon (target/hexagon) Remove PC from the runtime stateTaylor Simpson
Add pc field to Packet structure For helpers that need PC, pass an extra argument Remove slot arg from conditional jump helpers On a trap0, copy pkt->pc into hex_gpr[HEX_REG_PC] Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20221108162906.3166-6-tsimpson@quicinc.com>
2022-12-16Hexagon (target/hexagon) Only use branch_taken when packet has multi cofTaylor Simpson
When a packet has more than one change-of-flow instruction, only the first one to branch is considered. We use the branch_taken variable to keep track of this. However, when there is a single cof instruction, we don't need the same amount of bookkeeping. We add the pkt_has_multi_cof member to the Packet structure, and pass this information to the needed functions. When there is a generated helper function with cof, the generator will pass this pkt_has_multi_cof as a runtime value. Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20221108162906.3166-5-tsimpson@quicinc.com>
2022-09-30Hexagon (target/hexagon) Change decision to set pkt_has_store_s[01]Taylor Simpson
We have found cases where pkt_has_store_s[01] is set incorrectly. This leads to generating an unnecessary store that is left over from a previous packet. Add an attribute to determine if an instruction is a scalar store The attribute is attached to the fSTORE macro (hex_common.py) Update the logic in decode.c that sets pkt_has_store_s[01] Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220920080746.26791-4-tsimpson@quicinc.com>
2021-11-03Hexagon HVX (target/hexagon) semantics generatorTaylor Simpson
Add HVX support to the semantics generator Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
2021-10-28Hexagon (target/hexagon) put writes to USR into temp until commitTaylor Simpson
Change SET_USR_FIELD to write to hex_new_value[HEX_REG_USR] instead of hex_gpr[HEX_REG_USR]. Then, we need code to mark the instructions that can set implicitly set USR - Macros added to hex_common.py - A_FPOP added in translate.c Test case added in tests/tcg/hexagon/overflow.c Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
2021-02-18Hexagon (target/hexagon) generator phase 2 - generate header filesTaylor Simpson
Python scripts generate the following files helper_protos_generated.h.inc For each instruction we create DEF_HELPER function prototype helper_funcs_generated.c.inc For each instruction we create the helper function definition tcg_funcs_generated.c.inc For each instruction we create TCG code to generate call to helper tcg_func_table_generated.c.inc Table of function pointers indexed by opcode shortcode_generated.h.inc Generate a table of instruction "shortcode" semantics opcodes_def_generated.h.inc Gives a list of all the opcodes op_attribs_generated.h.inc Lists all the attributes associated with each instruction op_regs_generated.h.inc Lists the register and immediate operands for each instruction printinsn_generated.h.inc Data for printing (disassembling) each instruction (format string + operands) Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <1612763186-18161-21-git-send-email-tsimpson@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>