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AgeCommit message (Expand)Author
2021-05-26hw/core: Constify TCGCPUOpsRichard Henderson
2021-05-26cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOpsPhilippe Mathieu-Daudé
2021-05-26cpu: Introduce SysemuCPUOps structurePhilippe Mathieu-Daudé
2021-05-26cpu: Move AVR target vmsd field from CPUClass to DeviceClassPhilippe Mathieu-Daudé
2021-05-26cpu: Rename CPUClass vmsd -> legacy_vmsdPhilippe Mathieu-Daudé
2021-05-13target/avr: Ignore unimplemented WDR opcodePhilippe Mathieu-Daudé
2021-03-15target/avr: Fix interrupt executionIvanov Arkasha
2021-03-15target/avr: Fix some comment spelling errorsLichang Zhao
2021-02-20target/avr/cpu: Use device_class_set_parent_realize()Philippe Mathieu-Daudé
2021-02-05cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClassClaudio Fontana
2021-02-05cpu: move cc->do_interrupt to tcg_opsClaudio Fontana
2021-02-05cpu: Move tlb_fill to tcg_opsEduardo Habkost
2021-02-05cpu: Move cpu_exec_* to tcg_opsEduardo Habkost
2021-02-05cpu: Move synchronize_from_tb() to tcg_opsEduardo Habkost
2021-02-05cpu: Introduce TCGCpuOperations structEduardo Habkost
2021-01-07tcg: Make tb arg to synchronize_from_tb constRichard Henderson
2020-12-19migration: Replace migration's JSON writer by the general oneMarkus Armbruster
2020-09-18qom: Remove module_obj_name parameter from OBJECT_DECLARE* macrosEduardo Habkost
2020-09-09Use OBJECT_DECLARE_TYPE where possibleEduardo Habkost
2020-09-09Use DECLARE_*CHECKER* macrosEduardo Habkost
2020-09-09Move QOM typedefs and add missing includesEduardo Habkost
2020-08-21meson: targetPaolo Bonzini
2020-08-21meson: rename included C source files to .c.incPaolo Bonzini
2020-07-11target/avr/disas: Fix store instructions display orderPhilippe Mathieu-Daudé
2020-07-11target/avr/cpu: Fix $PC displayed addressPhilippe Mathieu-Daudé
2020-07-11target/avr/cpu: Drop tlb_flush() in avr_cpu_reset()Philippe Mathieu-Daudé
2020-07-11target/avr: Register AVR support with the rest of QEMUMichael Rolnik
2020-07-11target/avr: Add support for disassembling via option '-d in_asm'Michael Rolnik
2020-07-11target/avr: Initialize TCG register variablesMichael Rolnik
2020-07-11target/avr: Add instruction translation - CPU main translation functionMichael Rolnik
2020-07-11target/avr: Add instruction translation - MCU Control InstructionsMichael Rolnik
2020-07-11target/avr: Add instruction translation - Bit and Bit-test InstructionsMichael Rolnik
2020-07-11target/avr: Add instruction translation - Data Transfer InstructionsMichael Rolnik
2020-07-11target/avr: Add instruction translation - Branch InstructionsMichael Rolnik
2020-07-11target/avr: Add instruction translation - Arithmetic and Logic InstructionsMichael Rolnik
2020-07-11target/avr: Add instruction translation - Register definitionsMichael Rolnik
2020-07-11target/avr: Add instruction helpersMichael Rolnik
2020-07-10target/avr: Add definitions of AVR core typesMichael Rolnik
2020-07-10target/avr: Introduce enumeration AVRFeatureMichael Rolnik
2020-07-10target/avr: CPU class: Add GDB supportMichael Rolnik
2020-07-10target/avr: CPU class: Add migration supportMichael Rolnik
2020-07-10target/avr: CPU class: Add memory management supportMichael Rolnik
2020-07-10target/avr: CPU class: Add interrupt handling supportMichael Rolnik
2020-07-10target/avr: Introduce basic CPU class objectMichael Rolnik
2020-07-10target/avr: Add basic parameters of the new platformMichael Rolnik
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