slackcoder/qemu - QEMU is a generic and open source machine & userspace emulator and virtualizer

Age	Commit message (Expand)	Author
2023-03-13	target/avr: Avoid use of tcg_const_i32 throughout	Richard Henderson
2023-03-13	target/avr: Avoid use of tcg_const_i32 in SBIC, SBIS	Richard Henderson
2023-03-05	target/avr: Drop tcg_temp_free	Richard Henderson
2023-03-05	target/avr: Drop R from trans_COM	Richard Henderson
2023-03-05	target/avr: Drop DisasContext.free_skip_var0	Richard Henderson
2023-03-01	accel/tcg: Pass max_insn to gen_intermediate_code by pointer	Richard Henderson
2022-10-26	target/avr: Convert to tcg_ops restore_state_to_opc	Richard Henderson
2022-09-06	accel/tcg: Add pc and host_pc params to gen_intermediate_code	Richard Henderson
2022-09-01	target/avr: Disable interrupts when env->skip set	Richard Henderson
2022-04-20	exec/translator: Pass the locked filepointer to disas_log hook	Richard Henderson
2021-10-15	target/avr: Drop checks for singlestep_enabled	Richard Henderson
2021-09-16	target/avr: Fix compiler errors (-Werror=enum-conversion)	Stefan Weil
2021-07-21	accel/tcg: Remove TranslatorOps.breakpoint_check	Richard Henderson
2021-07-21	target/avr: Implement gdb_adjust_breakpoint	Richard Henderson
2021-07-09	target/avr: Use translator_use_goto_tb	Richard Henderson
2021-06-29	target/avr: Convert to TranslatorOps	Richard Henderson
2021-06-29	target/avr: Change ctx to DisasContext* in gen_intermediate_code	Richard Henderson
2021-06-29	target/avr: Add DisasContextBase to DisasContext	Richard Henderson
2020-08-21	meson: target	Paolo Bonzini
2020-08-21	meson: rename included C source files to .c.inc	Paolo Bonzini
2020-07-11	target/avr: Add support for disassembling via option '-d in_asm'	Michael Rolnik
2020-07-11	target/avr: Initialize TCG register variables	Michael Rolnik
2020-07-11	target/avr: Add instruction translation - CPU main translation function	Michael Rolnik
2020-07-11	target/avr: Add instruction translation - MCU Control Instructions	Michael Rolnik
2020-07-11	target/avr: Add instruction translation - Bit and Bit-test Instructions	Michael Rolnik
2020-07-11	target/avr: Add instruction translation - Data Transfer Instructions	Michael Rolnik
2020-07-11	target/avr: Add instruction translation - Branch Instructions	Michael Rolnik
2020-07-11	target/avr: Add instruction translation - Arithmetic and Logic Instructions	Michael Rolnik
2020-07-11	target/avr: Add instruction translation - Register definitions	Michael Rolnik