| Age | Commit message (Expand) | Author |
|---|
| 2017-09-07 | Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20170907'... | Peter Maydell |
| 2017-09-07 | target/arm: Add Jazelle feature | Portia Stephens |
| 2017-09-07 | target/arm: Implement new do_transaction_failed hook | Peter Maydell |
| 2017-09-07 | target/arm: Implement BXNS, and banked stack pointers | Peter Maydell |
| 2017-09-07 | target/arm: Move regime_is_secure() to target/arm/internals.h | Peter Maydell |
| 2017-09-07 | target/arm: Make CFSR register banked for v8M | Peter Maydell |
| 2017-09-07 | target/arm: Make MMFAR banked for v8M | Peter Maydell |
| 2017-09-07 | target/arm: Make CCR register banked for v8M | Peter Maydell |
| 2017-09-07 | target/arm: Make MPU_CTRL register banked for v8M | Peter Maydell |
| 2017-09-07 | target/arm: Make MPU_RNR register banked for v8M | Peter Maydell |
| 2017-09-07 | target/arm: Make MPU_RBAR, MPU_RLAR banked for v8M | Peter Maydell |
| 2017-09-07 | target/arm: Make MPU_MAIR0, MPU_MAIR1 registers banked for v8M | Peter Maydell |
| 2017-09-07 | target/arm: Make VTOR register banked for v8M | Peter Maydell |
| 2017-09-07 | target/arm: Make CONTROL register banked for v8M | Peter Maydell |
| 2017-09-07 | target/arm: Make FAULTMASK register banked for v8M | Peter Maydell |
| 2017-09-07 | target/arm: Make PRIMASK register banked for v8M | Peter Maydell |
| 2017-09-07 | target/arm: Make BASEPRI register banked for v8M | Peter Maydell |
| 2017-09-07 | target/arm: Add MMU indexes for secure v8M | Peter Maydell |
| 2017-09-07 | target/arm: Register second AddressSpace for secure v8M CPUs | Peter Maydell |
| 2017-09-07 | target/arm: Add state field, feature bit and migration for v8M secure state | Peter Maydell |
| 2017-09-07 | target/arm: Implement new PMSAv8 behaviour | Peter Maydell |
| 2017-09-07 | target/arm: Implement ARMv8M's PMSAv8 registers | Peter Maydell |
| 2017-09-06 | target/arm: Perform per-insn cross-page check only for Thumb | Richard Henderson |
| 2017-09-06 | target/arm: Split out thumb_tr_translate_insn | Richard Henderson |
| 2017-09-06 | target/arm: Move ss check to init_disas_context | Richard Henderson |
| 2017-09-06 | target/arm: [a64] Move page and ss checks to init_disas_context | Richard Henderson |
| 2017-09-06 | target/arm: [tcg] Port to generic translation framework | Lluís Vilanova |
| 2017-09-06 | target/arm: [tcg,a64] Port to disas_log | Lluís Vilanova |
| 2017-09-06 | target/arm: [tcg] Port to disas_log | Lluís Vilanova |
| 2017-09-06 | target/arm: [tcg,a64] Port to tb_stop | Lluís Vilanova |
| 2017-09-06 | target/arm: [tcg] Port to tb_stop | Lluís Vilanova |
| 2017-09-06 | target/arm: [tcg,a64] Port to translate_insn | Lluís Vilanova |
| 2017-09-06 | target/arm: [tcg] Port to translate_insn | Lluís Vilanova |
| 2017-09-06 | target/arm: [tcg,a64] Port to breakpoint_check | Lluís Vilanova |
| 2017-09-06 | target/arm: [tcg,a64] Port to insn_start | Lluís Vilanova |
| 2017-09-06 | target/arm: [tcg] Port to insn_start | Lluís Vilanova |
| 2017-09-06 | target/arm: [tcg] Port to tb_start | Lluís Vilanova |
| 2017-09-06 | target/arm: [tcg,a64] Port to init_disas_context | Lluís Vilanova |
| 2017-09-06 | target/arm: [tcg] Port to init_disas_context | Lluís Vilanova |
| 2017-09-06 | target/arm: [tcg] Port to DisasContextBase | Lluís Vilanova |
| 2017-09-06 | target/arm: Delay check for magic kernel page | Richard Henderson |
| 2017-09-06 | target: [tcg] Use a generic enum for DISAS_ values | Lluís Vilanova |
| 2017-09-06 | target/arm: Use DISAS_NORETURN | Richard Henderson |
| 2017-09-04 | target/arm: Fix aa64 ldp register writeback | Richard Henderson |
| 2017-09-04 | target/arm: Allow deliver_fault() caller to specify EA bit | Peter Maydell |
| 2017-09-04 | target/arm: Factor out fault delivery code | Peter Maydell |
| 2017-09-04 | target/arm/kvm: pmu: improve error handling | Andrew Jones |
| 2017-09-04 | hw/arm/virt: allow pmu instantiation with userspace irqchip | Andrew Jones |
| 2017-09-04 | target/arm/kvm: pmu: split init and set-irq stages | Andrew Jones |
| 2017-09-04 | hw/arm/virt: add pmu interrupt state | Andrew Jones |
