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QEMU is a generic and open source machine & userspace emulator and virtualizer
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arm
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2024-04-26
exec: Rename NEED_CPU_H -> COMPILING_PER_TARGET
Philippe Mathieu-Daudé
2024-04-25
hw, target: Add ResetType argument to hold and exit phase methods
Peter Maydell
2024-04-25
target/arm: Add FEAT_NMI to max
Jinjie Ruan
2024-04-25
target/arm: Handle NMI in arm_cpu_do_interrupt_aarch64()
Jinjie Ruan
2024-04-25
target/arm: Handle PSTATE.ALLINT on taking an exception
Jinjie Ruan
2024-04-25
target/arm: Handle IS/FS in ISR_EL1 for NMI, VINMI and VFNMI
Jinjie Ruan
2024-04-25
target/arm: Add support for NMI in arm_phys_excp_target_el()
Jinjie Ruan
2024-04-25
target/arm: Add support for Non-maskable Interrupt
Jinjie Ruan
2024-04-25
target/arm: Support MSR access to ALLINT
Jinjie Ruan
2024-04-25
target/arm: Implement ALLINT MSR (immediate)
Jinjie Ruan
2024-04-25
target/arm: Add support for FEAT_NMI, Non-maskable Interrupt
Jinjie Ruan
2024-04-25
target/arm: Add PSTATE.ALLINT
Jinjie Ruan
2024-04-25
target/arm: Handle HCR_EL2 accesses for bits introduced with FEAT_NMI
Jinjie Ruan
2024-04-23
KVM: remove kvm_arch_cpu_check_are_resettable
Paolo Bonzini
2024-04-09
target/arm: Use insn_start from DisasContextBase
Richard Henderson
2024-04-08
target/arm: Use correct SecuritySpace for AArch64 AT ops at EL3
Peter Maydell
2024-04-05
target/arm: Fix CNTPOFF_EL2 trap to missing EL3
Pierre-Clément Tosi
2024-04-02
accel/hvf: Un-inline hvf_arch_supports_guest_debug()
Philippe Mathieu-Daudé
2024-04-02
target/arm: take HSTR traps of cp15 accesses to EL2, not EL1
Peter Maydell
2024-03-12
Merge tag 'pull-error-2024-03-12' of https://repo.or.cz/qemu/armbru into staging
Peter Maydell
2024-03-12
target: Improve error reporting for CpuModelInfo member @props
Markus Armbruster
2024-03-12
target: Simplify type checks for CpuModelInfo member @props
Markus Armbruster
2024-03-12
target: Replace CPU_GET_CLASS(cpu -> obj) in cpu_reset_hold() handler
Philippe Mathieu-Daudé
2024-03-12
bulk: Access existing variables initialized to &S->F when available
Philippe Mathieu-Daudé
2024-03-08
target/arm: Move v7m-related code from cpu32.c into a separate file
Thomas Huth
2024-03-07
target/arm: Fix 32-bit SMOPA
Richard Henderson
2024-03-07
target/arm: Enable FEAT_ECV for 'max' CPU
Peter Maydell
2024-03-07
target/arm: Implement FEAT_ECV CNTPOFF_EL2 handling
Peter Maydell
2024-03-07
target/arm: Define CNTPCTSS_EL0 and CNTVCTSS_EL0
Peter Maydell
2024-03-07
target/arm: Implement new FEAT_ECV trap bits
Peter Maydell
2024-03-07
target/arm: Don't allow RES0 CNTHCTL_EL2 bits to be written
Peter Maydell
2024-03-07
target/arm: use FIELD macro for CNTHCTL bit definitions
Peter Maydell
2024-03-07
target/arm: Timer _EL02 registers UNDEF for E2H == 0
Peter Maydell
2024-03-07
target/arm: Move some register related defines to internals.h
Peter Maydell
2024-03-05
target/arm: Do memory type alignment check when translation enabled
Richard Henderson
2024-03-05
target/arm: Do memory type alignment check when translation disabled
Richard Henderson
2024-03-05
target/arm: Support 32-byte alignment in pow2_align
Richard Henderson
2024-02-29
target/arm: Enable TARGET_PAGE_BITS_VARY for AArch64 user-only
Richard Henderson
2024-02-28
hw/core/cpu: Remove gdb_get_dynamic_xml member
Akihiko Odaki
2024-02-28
gdbstub: Infer number of core registers from XML
Akihiko Odaki
2024-02-28
gdbstub: Change gdb_get_reg_cb and gdb_set_reg_cb
Akihiko Odaki
2024-02-28
gdbstub: Use GDBFeature for gdb_register_coprocessor
Akihiko Odaki
2024-02-28
target/arm: Use GDBFeature for dynamic XML
Akihiko Odaki
2024-02-27
arm/ptw: Handle atomic updates of page tables entries in MMIO during PTW.
Jonathan Cameron
2024-02-27
target/arm: Advertise Cortex-A53 erratum #843419 fix via REVIDR
Ard Biesheuvel
2024-02-15
target/arm: Allow access to SPSR_hyp from hyp mode
Peter Maydell
2024-02-15
target/arm: Add Cortex-R52 IMPDEF sysregs
Peter Maydell
2024-02-15
target/arm: The Cortex-R52 has a read-only CBAR
Peter Maydell
2024-02-15
target/arm: Use new CBAR encoding for all v8 CPUs, not all aarch64 CPUs
Peter Maydell
2024-02-15
target/arm: Don't get MDCR_EL2 in pmu_counter_enabled() before checking ARM_F...
Peter Maydell
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