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AgeCommit message (Expand)Author
2021-01-29target/arm: Replace magic value by MMU_DATA_LOAD definitionPhilippe Mathieu-Daudé
2021-01-29target/arm: Conditionalize DBGDIDRRichard Henderson
2021-01-29target/arm: Implement ID_PFR2Richard Henderson
2021-01-19target/arm/m_helper: Silence GCC 10 maybe-uninitialized errorPhilippe Mathieu-Daudé
2021-01-19target/arm: Update REV, PUNPK for pred_descRichard Henderson
2021-01-19target/arm: Update ZIP, UZP, TRN for pred_descRichard Henderson
2021-01-19target/arm: Update PFIRST, PNEXT for pred_descRichard Henderson
2021-01-19target/arm: Introduce PREDDESC field definitionsRichard Henderson
2021-01-19target/arm: refactor vae1_tlbmask()Rémi Denis-Courmont
2021-01-19target/arm: enable Secure EL2 in max CPURémi Denis-Courmont
2021-01-19target/arm: Implement SCR_EL2.EEL2Rémi Denis-Courmont
2021-01-19target/arm: revector to run-time pick target ELRémi Denis-Courmont
2021-01-19target/arm: set HPFAR_EL2.NS on secure stage 2 faultsRémi Denis-Courmont
2021-01-19target/arm: secure stage 2 translation regimeRémi Denis-Courmont
2021-01-19target/arm: generalize 2-stage page-walk conditionRémi Denis-Courmont
2021-01-19target/arm: translate NS bit in page-walksRémi Denis-Courmont
2021-01-19target/arm: do S1_ptw_translate() before address space lookupRémi Denis-Courmont
2021-01-19target/arm: handle VMID change in secure stateRémi Denis-Courmont
2021-01-19target/arm: add ARMv8.4-SEL2 system registersRémi Denis-Courmont
2021-01-19target/arm: add MMU stage 1 for Secure EL2Rémi Denis-Courmont
2021-01-19target/arm: add 64-bit S-EL2 to EL exception tableRémi Denis-Courmont
2021-01-19target/arm: Define isar_feature function to test for presence of SEL2Rémi Denis-Courmont
2021-01-19target/arm: factor MDCR_EL2 common handlingRémi Denis-Courmont
2021-01-19target/arm: use arm_hcr_el2_eff() where applicableRémi Denis-Courmont
2021-01-19target/arm: use arm_is_el2_enabled() where applicableRémi Denis-Courmont
2021-01-19target/arm: add arm_is_el2_enabled() helperRémi Denis-Courmont
2021-01-19target/arm: remove redundant testsRémi Denis-Courmont
2021-01-19target/arm: Use object_property_add_bool for "sve" propertyRichard Henderson
2021-01-19target/arm: Add cpu properties to control pauthRichard Henderson
2021-01-19target/arm: Implement an IMPDEF pauth algorithmRichard Henderson
2021-01-18semihosting: Change common-semi API to be architecture-independentKeith Packard
2021-01-18semihosting: Move ARM semihosting code to shared directoriesKeith Packard
2021-01-18target/arm: use official org.gnu.gdb.aarch64.sve layout for registersAlex Bennée
2021-01-18gdbstub: drop CPUEnv from gdb_exit()Alex Bennée
2021-01-12target/arm: Don't decode insns in the XScale/iWMMXt space as cp insnsPeter Maydell
2021-01-12target/arm: add aarch32 ID register fields to cpu.hLeif Lindholm
2021-01-12target/arm: add aarch64 ID register fields to cpu.hLeif Lindholm
2021-01-12target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.hLeif Lindholm
2021-01-12target/arm: make ARMCPU.ctr 64-bitLeif Lindholm
2021-01-12target/arm: make ARMCPU.clidr 64-bitLeif Lindholm
2021-01-12target/arm: fix typo in cpu.h ID_AA64PFR1 field nameLeif Lindholm
2021-01-12target/arm: enable Small Translation tables in max CPURémi Denis-Courmont
2021-01-12target/arm: ARMv8.4-TTST extensionRémi Denis-Courmont
2021-01-08target/arm: Remove timer_del()/timer_deinit() before timer_free()Peter Maydell
2021-01-08target/arm: Implement Cortex-M55 modelPeter Maydell
2021-01-08target/arm: Implement FPCXT_NS fp system registerPeter Maydell
2021-01-08target/arm: Correct store of FPSCR value via FPCXT_SPeter Maydell
2021-01-08target/arm: Fix MTE0_ACTIVERichard Henderson
2021-01-07tcg: Make tb arg to synchronize_from_tb constRichard Henderson
2021-01-07tcg: Make DisasContextBase.tb constRichard Henderson