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AgeCommit message (Expand)Author
2019-09-27target/arm: remove run time semihosting checksAlex Bennée
2019-09-27target/arm: handle A-profile semihosting at translate timeAlex Bennée
2019-09-27target/arm: handle M-profile semihosting at translate timeAlex Bennée
2019-09-27target/arm: fix CBAR register for AArch64 CPUsLuc Michel
2019-09-05target/arm: Inline gen_bx_im into callersRichard Henderson
2019-09-05target/arm: Clean up disas_thumb_insnRichard Henderson
2019-09-05target/arm: Convert T16, long branchesRichard Henderson
2019-09-05target/arm: Convert T16, Unconditional branchRichard Henderson
2019-09-05target/arm: Convert T16, load (literal)Richard Henderson
2019-09-05target/arm: Convert T16, shift immediateRichard Henderson
2019-09-05target/arm: Convert T16, Miscellaneous 16-bit instructionsRichard Henderson
2019-09-05target/arm: Convert T16, Conditional branches, Supervisor callRichard Henderson
2019-09-05target/arm: Convert T16, push and popRichard Henderson
2019-09-05target/arm: Split gen_nop_hintRichard Henderson
2019-09-05target/arm: Convert T16, nop hintsRichard Henderson
2019-09-05target/arm: Convert T16, Reverse bytesRichard Henderson
2019-09-05target/arm: Convert T16, Change processor stateRichard Henderson
2019-09-05target/arm: Convert T16, extractRichard Henderson
2019-09-05target/arm: Convert T16 adjust sp (immediate)Richard Henderson
2019-09-05target/arm: Convert T16 add, compare, move (two high registers)Richard Henderson
2019-09-05target/arm: Convert T16 branch and exchangeRichard Henderson
2019-09-05target/arm: Convert T16 one low register and immediateRichard Henderson
2019-09-05target/arm: Convert T16 add/sub (3 low, 2 low and imm)Richard Henderson
2019-09-05target/arm: Convert T16 load/store multipleRichard Henderson
2019-09-05target/arm: Convert T16 add pc/sp (immediate)Richard Henderson
2019-09-05target/arm: Convert T16 load/store (immediate offset)Richard Henderson
2019-09-05target/arm: Convert T16 load/store (register offset)Richard Henderson
2019-09-05target/arm: Convert T16 data-processing (two low regs)Richard Henderson
2019-09-05target/arm: Add skeleton for T16 decodetreeRichard Henderson
2019-09-05target/arm: Simplify disas_arm_insnRichard Henderson
2019-09-05target/arm: Simplify disas_thumb2_insnRichard Henderson
2019-09-05target/arm: Convert TTRichard Henderson
2019-09-05target/arm: Convert SGRichard Henderson
2019-09-05target/arm: Convert Table BranchRichard Henderson
2019-09-05target/arm: Convert Unallocated memory hintRichard Henderson
2019-09-05target/arm: Convert PLI, PLD, PLDWRichard Henderson
2019-09-05target/arm: Convert SETENDRichard Henderson
2019-09-05target/arm: Convert CPS (privileged)Richard Henderson
2019-09-05target/arm: Convert Clear-Exclusive, BarriersRichard Henderson
2019-09-05target/arm: Convert RFE and SRSRichard Henderson
2019-09-05target/arm: Convert SVCRichard Henderson
2019-09-05target/arm: Convert B, BL, BLX (immediate)Richard Henderson
2019-09-05target/arm: Diagnose base == pc for LDM/STMRichard Henderson
2019-09-05target/arm: Diagnose too few registers in list for LDM/STMRichard Henderson
2019-09-05target/arm: Diagnose writeback register in list for LDM for v7Richard Henderson
2019-09-05target/arm: Convert LDM, STMRichard Henderson
2019-09-05target/arm: Convert MOVW, MOVTRichard Henderson
2019-09-05target/arm: Convert Signed multiply, signed and unsigned divideRichard Henderson
2019-09-05target/arm: Convert packing, unpacking, saturation, and reversalRichard Henderson
2019-09-05target/arm: Convert Parallel addition and subtractionRichard Henderson