Age | Commit message (Expand) | Author |
2019-09-27 | target/arm: remove run time semihosting checks | Alex Bennée |
2019-09-27 | target/arm: handle A-profile semihosting at translate time | Alex Bennée |
2019-09-27 | target/arm: handle M-profile semihosting at translate time | Alex Bennée |
2019-09-27 | target/arm: fix CBAR register for AArch64 CPUs | Luc Michel |
2019-09-05 | target/arm: Inline gen_bx_im into callers | Richard Henderson |
2019-09-05 | target/arm: Clean up disas_thumb_insn | Richard Henderson |
2019-09-05 | target/arm: Convert T16, long branches | Richard Henderson |
2019-09-05 | target/arm: Convert T16, Unconditional branch | Richard Henderson |
2019-09-05 | target/arm: Convert T16, load (literal) | Richard Henderson |
2019-09-05 | target/arm: Convert T16, shift immediate | Richard Henderson |
2019-09-05 | target/arm: Convert T16, Miscellaneous 16-bit instructions | Richard Henderson |
2019-09-05 | target/arm: Convert T16, Conditional branches, Supervisor call | Richard Henderson |
2019-09-05 | target/arm: Convert T16, push and pop | Richard Henderson |
2019-09-05 | target/arm: Split gen_nop_hint | Richard Henderson |
2019-09-05 | target/arm: Convert T16, nop hints | Richard Henderson |
2019-09-05 | target/arm: Convert T16, Reverse bytes | Richard Henderson |
2019-09-05 | target/arm: Convert T16, Change processor state | Richard Henderson |
2019-09-05 | target/arm: Convert T16, extract | Richard Henderson |
2019-09-05 | target/arm: Convert T16 adjust sp (immediate) | Richard Henderson |
2019-09-05 | target/arm: Convert T16 add, compare, move (two high registers) | Richard Henderson |
2019-09-05 | target/arm: Convert T16 branch and exchange | Richard Henderson |
2019-09-05 | target/arm: Convert T16 one low register and immediate | Richard Henderson |
2019-09-05 | target/arm: Convert T16 add/sub (3 low, 2 low and imm) | Richard Henderson |
2019-09-05 | target/arm: Convert T16 load/store multiple | Richard Henderson |
2019-09-05 | target/arm: Convert T16 add pc/sp (immediate) | Richard Henderson |
2019-09-05 | target/arm: Convert T16 load/store (immediate offset) | Richard Henderson |
2019-09-05 | target/arm: Convert T16 load/store (register offset) | Richard Henderson |
2019-09-05 | target/arm: Convert T16 data-processing (two low regs) | Richard Henderson |
2019-09-05 | target/arm: Add skeleton for T16 decodetree | Richard Henderson |
2019-09-05 | target/arm: Simplify disas_arm_insn | Richard Henderson |
2019-09-05 | target/arm: Simplify disas_thumb2_insn | Richard Henderson |
2019-09-05 | target/arm: Convert TT | Richard Henderson |
2019-09-05 | target/arm: Convert SG | Richard Henderson |
2019-09-05 | target/arm: Convert Table Branch | Richard Henderson |
2019-09-05 | target/arm: Convert Unallocated memory hint | Richard Henderson |
2019-09-05 | target/arm: Convert PLI, PLD, PLDW | Richard Henderson |
2019-09-05 | target/arm: Convert SETEND | Richard Henderson |
2019-09-05 | target/arm: Convert CPS (privileged) | Richard Henderson |
2019-09-05 | target/arm: Convert Clear-Exclusive, Barriers | Richard Henderson |
2019-09-05 | target/arm: Convert RFE and SRS | Richard Henderson |
2019-09-05 | target/arm: Convert SVC | Richard Henderson |
2019-09-05 | target/arm: Convert B, BL, BLX (immediate) | Richard Henderson |
2019-09-05 | target/arm: Diagnose base == pc for LDM/STM | Richard Henderson |
2019-09-05 | target/arm: Diagnose too few registers in list for LDM/STM | Richard Henderson |
2019-09-05 | target/arm: Diagnose writeback register in list for LDM for v7 | Richard Henderson |
2019-09-05 | target/arm: Convert LDM, STM | Richard Henderson |
2019-09-05 | target/arm: Convert MOVW, MOVT | Richard Henderson |
2019-09-05 | target/arm: Convert Signed multiply, signed and unsigned divide | Richard Henderson |
2019-09-05 | target/arm: Convert packing, unpacking, saturation, and reversal | Richard Henderson |
2019-09-05 | target/arm: Convert Parallel addition and subtraction | Richard Henderson |