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2019-07-04target/arm: Use _ra versions of cpu_stl_data() in v7M helpersPeter Maydell
In the various helper functions for v7M/v8M instructions, use the _ra versions of cpu_stl_data() and friends. Otherwise we may get wrong behaviour or an assert() due to not being able to locate the TB if there is an exception on the memory access or if it performs an IO operation when in icount mode. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190617175317.27557-5-peter.maydell@linaro.org
2019-07-04target/arm/helper: Move M profile routines to m_helper.cPhilippe Mathieu-Daudé
In preparation for supporting TCG disablement on ARM, we move most of TCG related v7m/v8m helpers and APIs into their own file. Note: It is easier to review this commit using the 'histogram' diff algorithm: $ git diff --diff-algorithm=histogram ... or $ git diff --histogram ... Suggested-by: Samuel Ortiz <sameo@linux.intel.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190702144335.10717-2-philmd@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: updated qapi #include to match recent changes there] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-04target/arm: Restrict semi-hosting to TCGPhilippe Mathieu-Daudé
Per Peter Maydell: Semihosting hooks either SVC or HLT instructions, and inside KVM both of those go to EL1, ie to the guest, and can't be trapped to KVM. Let check_for_semihosting() return False when not running on TCG. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190701194942.10092-3-philmd@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-04target/arm: Move debug routines to debug_helper.cPhilippe Mathieu-Daudé
These routines are TCG specific. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190701194942.10092-2-philmd@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-03Merge remote-tracking branch ↵Peter Maydell
'remotes/armbru/tags/pull-monitor-2019-07-02-v2' into staging Monitor patches for 2019-07-02 # gpg: Signature made Tue 02 Jul 2019 12:37:57 BST # gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653 # gpg: issuer "armbru@redhat.com" # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full] # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" [full] # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653 * remotes/armbru/tags/pull-monitor-2019-07-02-v2: dump: Move HMP command handlers to dump/ MAINTAINERS: Add Windows dump to section "Dump" dump: Move the code to dump/ qapi: Split dump.json off misc.json qapi: Rename target.json to misc-target.json qapi: Split machine-target.json off target.json and misc.json hw/core: Collect HMP command handlers in hw/core/ hw/core: Collect QMP command handlers in hw/core/ hw/core: Move numa.c to hw/core/ qapi: Split machine.json off misc.json MAINTAINERS: Merge sections CPU, NUMA into Machine core qom: Move HMP command handlers to qom/ qom: Move QMP command handlers to qom/ qapi: Split qom.json and qdev.json off misc.json hmp: Move hmp.h to include/monitor/ Makefile: Don't add monitor/ twice to common-obj-y MAINTAINERS: Make section "QOM" cover qdev as well MAINTAINERS: new maintainers for QOM Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-02qapi: Rename target.json to misc-target.jsonMarkus Armbruster
Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190619201050.19040-14-armbru@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
2019-07-02qapi: Split machine-target.json off target.json and misc.jsonMarkus Armbruster
Move commands query-cpu-definitions, query-cpu-model-baseline, query-cpu-model-comparison, and query-cpu-model-expansion with their types from target.json to machine-target.json. Also move types CpuModelInfo, CpuModelExpansionType, and CpuModelCompareResult from misc.json there. Add machine-target.json to MAINTAINERS section "Machine core". Cc: Eduardo Habkost <ehabkost@redhat.com> Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20190619201050.19040-13-armbru@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> [Commit message typo fixed]
2019-07-01target/arm: Declare some M-profile functions publiclyPhilippe Mathieu-Daudé
In the next commit we will split the M-profile functions from this file. Some function will be called out of helper.c. Declare them in the "internals.h" header. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190701132516.26392-22-philmd@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-01target/arm: Declare arm_log_exception() function publiclyPhilippe Mathieu-Daudé
In few commits we will split the M-profile functions from this file, and this function will also be called in the new file. Declare it in the "internals.h" header. Since it is in the middle of a block of M profile functions, move it previous to this block to ease the later refactor. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190701132516.26392-21-philmd@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-01target/arm: Restrict PSCI to TCGPhilippe Mathieu-Daudé
Under KVM, the kernel gets the HVC call and handle the PSCI requests. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190701132516.26392-20-philmd@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-01target/arm/vfp_helper: Restrict the SoftFloat use to TCGPhilippe Mathieu-Daudé
This code is specific to the SoftFloat floating-point implementation, which is only used by TCG. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190701132516.26392-18-philmd@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-01target/arm/vfp_helper: Extract vfp_set_fpscr_from_host()Philippe Mathieu-Daudé
The vfp_set_fpscr() helper contains code specific to the host floating point implementation (here the SoftFloat library). Extract this code to vfp_set_fpscr_from_host(). Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190701132516.26392-17-philmd@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-01target/arm/vfp_helper: Extract vfp_set_fpscr_to_host()Philippe Mathieu-Daudé
The vfp_set_fpscr() helper contains code specific to the host floating point implementation (here the SoftFloat library). Extract this code to vfp_set_fpscr_to_host(). Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190701132516.26392-16-philmd@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-01target/arm/vfp_helper: Move code aroundPhilippe Mathieu-Daudé
To ease the review of the next commit, move the vfp_exceptbits_to_host() function directly after vfp_exceptbits_from_host(). Amusingly the diff shows we are moving vfp_get_fpscr(). Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190701132516.26392-15-philmd@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-01target/arm: Move TLB related routines to tlb_helper.cPhilippe Mathieu-Daudé
These routines are TCG specific. The arm_deliver_fault() function is only used within the new helper. Make it static. Suggested-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190701132516.26392-13-philmd@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-01target/arm: Declare get_phys_addr() function publiclyPhilippe Mathieu-Daudé
In the next commit we will split the TLB related routines of this file, and this function will also be called in the new file. Declare it in the "internals.h" header. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190701132516.26392-12-philmd@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-01target/arm: Move CPU state dumping routines to cpu.cPhilippe Mathieu-Daudé
Suggested-by: Samuel Ortiz <sameo@linux.intel.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190701132516.26392-11-philmd@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-01target/arm: Move the DC ZVA helper into op_helperSamuel Ortiz
Those helpers are a software implementation of the ARM v8 memory zeroing op code. They should be moved to the op helper file, which is going to eventually be built only when TCG is enabled. Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Robert Bradford <robert.bradford@intel.com> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190701132516.26392-10-philmd@redhat.com [PMD: Rebased] Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-01target/arm: Fix coding style issuesPhilippe Mathieu-Daudé
Since we'll move this code around, fix its style first. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190701132516.26392-9-philmd@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-01target/arm: Fix multiline comment syntaxPhilippe Mathieu-Daudé
Since commit 8c06fbdf36b checkpatch.pl enforce a new multiline comment syntax. Since we'll move this code around, fix its style first. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190701132516.26392-8-philmd@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-01target/arm/helper: Remove unused includePhilippe Mathieu-Daudé
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190701132516.26392-7-philmd@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-01target/arm: Add copyright boilerplatePhilippe Mathieu-Daudé
Reviewed-by: Robert Bradford <robert.bradford@intel.com> Reviewed-by: Samuel Ortiz <sameo@linux.intel.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190701132516.26392-6-philmd@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-01target/arm: Makefile cleanup (softmmu)Philippe Mathieu-Daudé
Group SOFTMMU objects together. Since PSCI is TCG specific, keep it separate. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190701132516.26392-5-philmd@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-01target/arm: Makefile cleanup (KVM)Philippe Mathieu-Daudé
Group KVM rules together. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190701132516.26392-4-philmd@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-01target/arm: Makefile cleanup (ARM)Philippe Mathieu-Daudé
Group ARM objects together, TCG related ones at the bottom. This will help when restricting TCG-only objects. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190701132516.26392-3-philmd@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-07-01target/arm: Makefile cleanup (Aarch64)Philippe Mathieu-Daudé
Group Aarch64 rules together, TCG related ones at the bottom. This will help when restricting TCG-only objects. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190701132516.26392-2-philmd@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-06-21KVM: Introduce kvm_arch_destroy_vcpu()Liran Alon
Simiar to how kvm_init_vcpu() calls kvm_arch_init_vcpu() to perform arch-dependent initialisation, introduce kvm_arch_destroy_vcpu() to be called from kvm_destroy_vcpu() to perform arch-dependent destruction. This was added because some architectures (Such as i386) currently do not free memory that it have allocated in kvm_arch_init_vcpu(). Suggested-by: Maran Wilson <maran.wilson@oracle.com> Reviewed-by: Maran Wilson <maran.wilson@oracle.com> Signed-off-by: Liran Alon <liran.alon@oracle.com> Message-Id: <20190619162140.133674-3-liran.alon@oracle.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-06-18target/arm: Check for dp support for dp VFM, not spPeter Maydell
In commit 1120827fa182f0e7622 we accidentally put the "UNDEF unless FPU has double-precision support" check in the single-precision VFM function. Put it in the dp function where it belongs. Fixes: 1120827fa182f0e7622 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190617160130.3207-1-peter.maydell@linaro.org
2019-06-17target/arm: Only implement doubles if the FPU supports themPeter Maydell
The architecture permits FPUs which have only single-precision support, not double-precision; Cortex-M4 and Cortex-M33 are both like that. Add the necessary checks on the MVFR0 FPDP field so that we UNDEF any double-precision instructions on CPUs like this. Note that even if FPDP==0 the insns like VMOV-to/from-gpreg, VLDM/VSTM, VLDR/VSTR which take double precision registers still exist. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190614104457.24703-3-peter.maydell@linaro.org
2019-06-17target/arm: Fix typos in trans function prototypesPeter Maydell
In several places cut and paste errors meant we were using the wrong type for the 'arg' struct in trans_ functions called by the decodetree decoder, because we were using the _sp version of the struct in the _dp function. These were harmless, because the two structs were identical and so decodetree made them typedefs of the same underlying structure (and we'd have had a compile error if they were not harmless), but we should clean them up anyway. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190614104457.24703-2-peter.maydell@linaro.org
2019-06-17target/arm: Remove unused cpu_F0s, cpu_F0d, cpu_F1s, cpu_F1dPeter Maydell
Remove the now unused TCG globals cpu_F0s, cpu_F0d, cpu_F1s, cpu_F1d. cpu_M0 is still used by the iwmmxt code, and cpu_V0 and cpu_V1 are used by both iwmmxt and Neon. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190613163917.28589-13-peter.maydell@linaro.org
2019-06-17target/arm: Stop using deprecated functions in NEON_2RM_VCVT_F32_F16Peter Maydell
Remove some old constructns from NEON_2RM_VCVT_F16_F32 code: * don't use CPU_F0s * don't use tcg_gen_st_f32 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190613163917.28589-12-peter.maydell@linaro.org
2019-06-17target/arm: stop using deprecated functions in NEON_2RM_VCVT_F16_F32Peter Maydell
Remove some old constructs from NEON_2RM_VCVT_F16_F32 code: * don't use cpu_F0s * don't use tcg_gen_ld_f32 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190613163917.28589-11-peter.maydell@linaro.org
2019-06-17target/arm: Stop using cpu_F0s in Neon VCVT fixed-point opsPeter Maydell
Stop using cpu_F0s in the Neon VCVT fixed-point operations. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190613163917.28589-10-peter.maydell@linaro.org
2019-06-17target/arm: Stop using cpu_F0s for Neon f32/s32 VCVTPeter Maydell
Stop using cpu_F0s for the Neon f32/s32 VCVT operations. Since this is the last user of cpu_F0s in the Neon 2rm-op loop, we can remove the handling code for it too. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190613163917.28589-9-peter.maydell@linaro.org
2019-06-17target/arm: Stop using cpu_F0s for NEON_2RM_VRECPE_F and NEON_2RM_VRSQRTE_FPeter Maydell
Stop using cpu_F0s for NEON_2RM_VRECPE_F and NEON_2RM_VRSQRTE_F. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190613163917.28589-8-peter.maydell@linaro.org
2019-06-17target/arm: Stop using cpu_F0s for NEON_2RM_VCVT[ANPM][US]Peter Maydell
Stop using cpu_F0s for the NEON_2RM_VCVT[ANPM][US] ops. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190613163917.28589-7-peter.maydell@linaro.org
2019-06-17target/arm: Stop using cpu_F0s for NEON_2RM_VRINT*Peter Maydell
Switch NEON_2RM_VRINT* away from using cpu_F0s. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190613163917.28589-6-peter.maydell@linaro.org
2019-06-17target/arm: Stop using cpu_F0s for NEON_2RM_VNEG_FPeter Maydell
Switch NEON_2RM_VABS_F away from using cpu_F0s. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190613163917.28589-5-peter.maydell@linaro.org
2019-06-17target/arm: Stop using cpu_F0s for NEON_2RM_VABS_FPeter Maydell
Where Neon instructions are floating point operations, we mostly use the old VFP utility functions like gen_vfp_abs() which work on the TCG globals cpu_F0s and cpu_F1s. The Neon for-each-element loop conditionally loads the inputs into either a plain old TCG temporary for most operations or into cpu_F0s for float operations, and similarly stores back either cpu_F0s or the temporary. Switch NEON_2RM_VABS_F away from using cpu_F0s, and update neon_2rm_is_float_op() accordingly. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190613163917.28589-4-peter.maydell@linaro.org
2019-06-17target/arm: Use vfp_expand_imm() for AArch32 VFP VMOV_immPeter Maydell
The AArch32 VMOV (immediate) instruction uses the same VFP encoded immediate format we already handle in vfp_expand_imm(). Use that function rather than hand-decoding it. Suggested-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190613163917.28589-3-peter.maydell@linaro.org
2019-06-17target/arm: Move vfp_expand_imm() to translate.[ch]Peter Maydell
We want to use vfp_expand_imm() in the AArch32 VFP decode; move it from the a64-only header/source file to the AArch32 one (which is always compiled even for AArch64). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190613163917.28589-2-peter.maydell@linaro.org
2019-06-17target/arm: Allow M-profile CPUs to disable the DSP extension via CPU propertyPeter Maydell
Allow the DSP extension to be disabled via a CPU property for M-profile CPUs. (A and R-profile CPUs don't have this extension as a defined separate optional architecture extension, so they don't need the property.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20190517174046.11146-3-peter.maydell@linaro.org
2019-06-17target/arm: Allow VFP and Neon to be disabled via a CPU propertyPeter Maydell
Allow VFP and neon to be disabled via a CPU property. As with the "pmu" property, we only allow these features to be removed from CPUs which have it by default, not added to CPUs which don't have it. The primary motivation here is to be able to optionally create Cortex-M33 CPUs with no FPU, but we provide switches for both VFP and Neon because the two interact: * AArch64 can't have one without the other * Some ID register fields only change if both are disabled Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20190517174046.11146-2-peter.maydell@linaro.org
2019-06-13target/arm: Fix short-vector increment behaviourPeter Maydell
For VFP short vectors, the VFP registers are divided into a series of banks: for single-precision these are s0-s7, s8-s15, s16-s23 and s24-s31; for double-precision they are d0-d3, d4-d7, ... d28-d31. Some banks are "scalar" meaning that use of a register within them triggers a pure-scalar or mixed vector-scalar operation rather than a full vector operation. The scalar banks are s0-s7, d0-d3 and d16-d19. When using a bank as part of a vector operation, we iterate through it, increasing the register number by the specified stride each time, and wrapping around to the beginning of the bank. Unfortunately our calculation of the "increment" part of this was incorrect: vd = ((vd + delta_d) & (bank_mask - 1)) | (vd & bank_mask) will only do the intended thing if bank_mask has exactly one set high bit. For instance for doubles (bank_mask = 0xc), if we start with vd = 6 and delta_d = 2 then vd is updated to 12 rather than the intended 4. This only causes problems in the unlikely case that the starting register is not the first in its bank: if the register number doesn't have to wrap around then the expression happens to give the right answer. Fix this bug by abstracting out the "check whether register is in a scalar bank" and "advance register within bank" operations to utility functions which use the right bit masking operations. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-06-13target/arm: Convert float-to-integer VCVT insns to decodetreePeter Maydell
Convert the float-to-integer VCVT instructions to decodetree. Since these are the last unconverted instructions, we can delete the old decoder structure entirely now. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-06-13target/arm: Convert VCVT fp/fixed-point conversion insns to decodetreePeter Maydell
Convert the VCVT (between floating-point and fixed-point) instructions to decodetree. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-06-13target/arm: Convert VJCVT to decodetreePeter Maydell
Convert the VJCVT instruction to decodetree. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-06-13target/arm: Convert integer-to-float insns to decodetreePeter Maydell
Convert the VCVT integer-to-float instructions to decodetree. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-06-13target/arm: Convert double-single precision conversion insns to decodetreePeter Maydell
Convert the VCVT double/single precision conversion insns to decodetree. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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