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2017-01-20target/arm/psci.c: If EL2 implemented, start CPUs in EL2Peter Maydell
The PSCI spec states that a CPU_ON call should cause the new CPU to be started in the highest implemented Non-secure exception level. We were incorrectly starting it at the exception level of the caller, which happens to be correct if EL2 is not implemented. Implement the correct logic as described in the PSCI 1.0 spec section 6.4: * if EL2 exists and SCR_EL3.HCE is set: start in EL2 * otherwise start in EL1 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Andrew Jones <drjones@redhat.com> Tested-by: Andrew Jones <drjones@redhat.com> Message-id: 1483977924-14522-17-git-send-email-peter.maydell@linaro.org
2017-01-20target-arm: Add ARMCPU fields for GIC CPU i/f configPeter Maydell
Add fields to the ARMCPU structure to allow CPU classes to specify the configurable aspects of their GIC CPU interface. In particular, the virtualization support allows different values for number of list registers, priority bits and preemption bits. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Alistair Francis <alistair.francis@xilinx.com> Message-id: 1483977924-14522-6-git-send-email-peter.maydell@linaro.org
2017-01-20target-arm: Expose output GPIO line for VCPU maintenance interruptPeter Maydell
The GICv3 support for virtualization includes an outbound maintenance interrupt signal which is asserted when the CPU interface wants to signal to the hypervisor that it needs attention. Expose this as an outbound GPIO line from the CPU object which can be wired up as a physical interrupt line by the board code (as we do already for the CPU timers). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-id: 1483977924-14522-4-git-send-email-peter.maydell@linaro.org
2017-01-20target/arm: Implement DBGVCR32_EL2 system registerPeter Maydell
The DBGVCR_EL2 system register is needed to run a 32-bit EL1 guest under a Linux EL2 64-bit hypervisor. Its only purpose is to provide AArch64 with access to the state of the DBGVCR AArch32 register. Since we only have a dummy DBGVCR, implement a corresponding dummy DBGVCR32_EL2. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2017-01-20target/arm: Handle VIRQ and VFIQ in arm_cpu_do_interrupt_aarch32()Peter Maydell
To run a VM in 32-bit EL1 our AArch32 interrupt handling code needs to be able to cope with VIRQ and VFIQ exceptions. These behave like IRQ and FIQ except that we don't need to try to route them to Monitor mode. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2017-01-19kvm: move cpu synchronization codeVincent Palatin
Move the generic cpu_synchronize_ functions to the common hw_accel.h header, in order to prepare for the addition of a second hardware accelerator. Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Message-Id: <f5c3cffe8d520011df1c2e5437bb814989b48332.1484045952.git.vpalatin@chromium.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2017-01-16Merge remote-tracking branch ↵Peter Maydell
'remotes/stsquad/tags/pull-tcg-common-tlb-reset-20170113-r1' into staging This is the same as the v3 posted except a re-base and a few extra signoffs # gpg: Signature made Fri 13 Jan 2017 14:26:46 GMT # gpg: using RSA key 0xFBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * remotes/stsquad/tags/pull-tcg-common-tlb-reset-20170113-r1: cputlb: drop flush_global flag from tlb_flush cpu_common_reset: wrap TCG specific code in tcg_enabled() qom/cpu: move tlb_flush to cpu_common_reset Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-13target/arm: Fix ubfx et al for aarch64Richard Henderson
The patch in 59a71b4c5b4e suffered from a merge failure when compared to the original patch in http://lists.nongnu.org/archive/html/qemu-devel/2016-12/msg00137.html Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-13Merge remote-tracking branch ↵Peter Maydell
'remotes/ehabkost/tags/x86-and-machine-pull-request' into staging x86 and machine queue, 2017-01-17 Includes i386, CPU, NUMA, and memory backends changes. i386: target/i386: Fix bad patch application to translate.c CPU: qmp: Report QOM type name on query-cpu-definitions NUMA: numa: make -numa parser dynamically allocate CPUs masks Memory backends: qom: remove unused header monitor: reuse user_creatable_add_opts() instead of user_creatable_add() monitor: fix qmp/hmp query-memdev not reporting IDs of memory backends # gpg: Signature made Thu 12 Jan 2017 17:53:11 GMT # gpg: using RSA key 0x2807936F984DC5A6 # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/x86-and-machine-pull-request: qmp: Report QOM type name on query-cpu-definitions numa: make -numa parser dynamically allocate CPUs masks target/i386: Fix bad patch application to translate.c monitor: fix qmp/hmp query-memdev not reporting IDs of memory backends monitor: reuse user_creatable_add_opts() instead of user_creatable_add() qom: remove unused header Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-01-13cputlb: drop flush_global flag from tlb_flushAlex Bennée
We have never has the concept of global TLB entries which would avoid the flush so we never actually use this flag. Drop it and make clear that tlb_flush is the sledge-hammer it has always been. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> [DG: ppc portions] Acked-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-13qom/cpu: move tlb_flush to cpu_common_resetAlex Bennée
It is a common thing amongst the various cpu reset functions want to flush the SoftMMU's TLB entries. This is done either by calling tlb_flush directly or by way of a general memset of the CPU structure (sometimes both). This moves the tlb_flush call to the common reset function and additionally ensures it is only done for the CONFIG_SOFTMMU case and when tcg is enabled. In some target cases we add an empty end_of_reset_fields structure to the target vCPU structure so have a clear end point for any memset which is resetting value in the structure before CPU_COMMON (where the TLB structures are). While this is a nice clean-up in general it is also a precursor for changes coming to cputlb for MTTCG where the clearing of entries can't be done arbitrarily across vCPUs. Currently the cpu_reset function is usually called from the context of another vCPU as the architectural power up sequence is run. By using the cputlb API functions we can ensure the right behaviour in the future. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
2017-01-12qmp: Report QOM type name on query-cpu-definitionsEduardo Habkost
The new typename attribute on query-cpu-definitions will be used to help management software use device-list-properties to check which properties can be set using -cpu or -global for the CPU model. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <1479320499-29818-1-git-send-email-ehabkost@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2017-01-10target-arm: Use clrsb helperRichard Henderson
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10target-arm: Use clz opcodeRichard Henderson
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-01-10target-arm: Use new deposit and extract opsRichard Henderson
Use the new primitives for UBFX and SBFX. Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-12-27target-arm: Add VBAR support to ARM1176 CPUsCédric Le Goater
ARM1176 CPUs have TrustZone support and can use the Vector Base Address Register, but currently, qemu only adds VBAR support to ARMv7 CPUs. Fix this by adding a new feature ARM_FEATURE_VBAR which can used for ARMv7 and ARM1176 CPUs. The VBAR feature is always set for ARMv7 because some legacy boards require it even if this is not architecturally correct. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 1481810970-9692-1-git-send-email-clg@kaod.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-12-27target-arm: Log AArch64 exception returnsPeter Maydell
We already log exception entry; add logging of the AArch64 exception return path as well. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-12-27target-arm: Fix aarch64 disas_ldst_single_structRichard Henderson
We add s->be_data within do_vec_ld/st. Adding it here means that we have the wrong bits set in SIZE for a big-endian host, leading to g_assert_not_reached in write_vec_element and read_vec_element. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-id: 1481085020-2614-3-git-send-email-rth@twiddle.net Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-12-27target-arm: Fix aarch64 vec_reg_offsetRichard Henderson
Since CPUARMState.vfp.regs is not 16 byte aligned, the ^ 8 fixup used for a big-endian host doesn't do what's intended. Fix this by adding in the vfp.regs offset after computing the inter-register offset. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-id: 1481085020-2614-2-git-send-email-rth@twiddle.net Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-12-27Correct value of ARM Cortex-A8 MVFR1 register.Julian Brown
The value of the MVFR1 (Media and VFP Feature Register 1) register for the Cortex-A8 appears to be incorrect (according to the TRM, DDI0344K), with the "full denormal arithmetic" and "propagation of NaN" fields holding both 0 instead of both 1. I had a go tracing the history of the use of this value, and it seems it's always just been wrong in QEMU: maybe it was derived from early documentation, or guessed based on the use of a "VFP Lite" implementation in the Cortex-A8. Depending on the startup/early-boot code in use, this can manifest as failure to perform denormal arithmetic properly: in our case, selecting a Cortex-A8 CPU when using QEMU as an instruction-set simulator for bare-metal GCC testing caused tests using denormal arithmetic to fail. Problems might be masked (or not occur) when using a full OS kernel with suitable trap handlers (I'm not sure). Signed-off-by: Julian Brown <julian@codesourcery.com> Message-id: 1481130858-31767-1-git-send-email-julian@codesourcery.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-12-20Move target-* CPU file into a target/ folderThomas Huth
We've currently got 18 architectures in QEMU, and thus 18 target-xxx folders in the root folder of the QEMU source tree. More architectures (e.g. RISC-V, AVR) are likely to be included soon, too, so the main folder of the QEMU sources slowly gets quite overcrowded with the target-xxx folders. To disburden the main folder a little bit, let's move the target-xxx folders into a dedicated target/ folder, so that target-xxx/ simply becomes target/xxx/ instead. Acked-by: Laurent Vivier <laurent@vivier.eu> [m68k part] Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> [tricore part] Acked-by: Michael Walle <michael@walle.cc> [lm32 part] Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> [s390x part] Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> [s390x part] Acked-by: Eduardo Habkost <ehabkost@redhat.com> [i386 part] Acked-by: Artyom Tarasenko <atar4qemu@gmail.com> [sparc part] Acked-by: Richard Henderson <rth@twiddle.net> [alpha part] Acked-by: Max Filippov <jcmvbkbc@gmail.com> [xtensa part] Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [ppc part] Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> [cris&microblaze part] Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn> [unicore32 part] Signed-off-by: Thomas Huth <thuth@redhat.com>
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