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AgeCommit message (Expand)Author
2017-09-23Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell
2017-09-22memory: Get rid of address_space_init_shareableAlexey Kardashevskiy
2017-09-21target/arm: Remove out of date ARM ARM section references in A64 decoderPeter Maydell
2017-09-21nvic: Support banked exceptions in acknowledge and completePeter Maydell
2017-09-21target/arm: Handle banking in negative-execution-priority check in cpu_mmu_in...Peter Maydell
2017-09-21nvic: Make set_pending and clear_pending take a secure parameterPeter Maydell
2017-09-21nvic: Implement AIRCR changes for v8MPeter Maydell
2017-09-21target/arm: Implement MSR/MRS access to NS banked registersPeter Maydell
2017-09-19arm: drop intermediate cpu_model -> cpu type parsing and use cpu type directlyIgor Mammedov
2017-09-14target/arm: Avoid an extra temporary for store_exclusiveRichard Henderson
2017-09-14AArch64: Fix single stepping of ERET instructionJaroslaw Pelczar
2017-09-14target/arm: Rename 'type' to 'excret' in do_v7m_exception_exit()Peter Maydell
2017-09-14target/arm: Add and use defines for EXCRET constantsPeter Maydell
2017-09-14target/arm: Remove unnecessary '| 0xf0000000' from do_v7m_exception_exit()Peter Maydell
2017-09-14target/arm: Get PRECISERR and IBUSERR the right way roundPeter Maydell
2017-09-14target/arm: Clear exclusive monitor on v7M reset, exception entry/exitPeter Maydell
2017-09-14target/arm: Use M_REG_NUM_BANKS rather than hardcoding 2Peter Maydell
2017-09-14hmp: fix "dump-quest-memory" segfault (arm)Laurent Vivier
2017-09-07Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20170907'...Peter Maydell
2017-09-07target/arm: Add Jazelle featurePortia Stephens
2017-09-07target/arm: Implement new do_transaction_failed hookPeter Maydell
2017-09-07target/arm: Implement BXNS, and banked stack pointersPeter Maydell
2017-09-07target/arm: Move regime_is_secure() to target/arm/internals.hPeter Maydell
2017-09-07target/arm: Make CFSR register banked for v8MPeter Maydell
2017-09-07target/arm: Make MMFAR banked for v8MPeter Maydell
2017-09-07target/arm: Make CCR register banked for v8MPeter Maydell
2017-09-07target/arm: Make MPU_CTRL register banked for v8MPeter Maydell
2017-09-07target/arm: Make MPU_RNR register banked for v8MPeter Maydell
2017-09-07target/arm: Make MPU_RBAR, MPU_RLAR banked for v8MPeter Maydell
2017-09-07target/arm: Make MPU_MAIR0, MPU_MAIR1 registers banked for v8MPeter Maydell
2017-09-07target/arm: Make VTOR register banked for v8MPeter Maydell
2017-09-07target/arm: Make CONTROL register banked for v8MPeter Maydell
2017-09-07target/arm: Make FAULTMASK register banked for v8MPeter Maydell
2017-09-07target/arm: Make PRIMASK register banked for v8MPeter Maydell
2017-09-07target/arm: Make BASEPRI register banked for v8MPeter Maydell
2017-09-07target/arm: Add MMU indexes for secure v8MPeter Maydell
2017-09-07target/arm: Register second AddressSpace for secure v8M CPUsPeter Maydell
2017-09-07target/arm: Add state field, feature bit and migration for v8M secure statePeter Maydell
2017-09-07target/arm: Implement new PMSAv8 behaviourPeter Maydell
2017-09-07target/arm: Implement ARMv8M's PMSAv8 registersPeter Maydell
2017-09-06target/arm: Perform per-insn cross-page check only for ThumbRichard Henderson
2017-09-06target/arm: Split out thumb_tr_translate_insnRichard Henderson
2017-09-06target/arm: Move ss check to init_disas_contextRichard Henderson
2017-09-06target/arm: [a64] Move page and ss checks to init_disas_contextRichard Henderson
2017-09-06target/arm: [tcg] Port to generic translation frameworkLluís Vilanova
2017-09-06target/arm: [tcg,a64] Port to disas_logLluís Vilanova
2017-09-06target/arm: [tcg] Port to disas_logLluís Vilanova
2017-09-06target/arm: [tcg,a64] Port to tb_stopLluís Vilanova
2017-09-06target/arm: [tcg] Port to tb_stopLluís Vilanova
2017-09-06target/arm: [tcg,a64] Port to translate_insnLluís Vilanova
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