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path: root/target/arm/translate-a64.c
AgeCommit message (Expand)Author
2018-03-23arm/translate-a64: treat DISAS_UPDATE as variant of DISAS_EXITVictor Kamensky
2018-03-02target/arm: Decode aa64 armv8.3 fcmlaRichard Henderson
2018-03-02target/arm: Decode aa64 armv8.3 fcaddRichard Henderson
2018-03-02target/arm: Decode aa64 armv8.1 scalar/vector x indexed elementRichard Henderson
2018-03-02target/arm: Decode aa64 armv8.1 three same extraRichard Henderson
2018-03-02target/arm: Decode aa64 armv8.1 scalar three same extraRichard Henderson
2018-03-02target/arm: Refactor disas_simd_indexed size checksRichard Henderson
2018-03-02target/arm: Refactor disas_simd_indexed decodeRichard Henderson
2018-03-01arm/translate-a64: add all single op FP16 to handle_fp_1src_halfAlex Bennée
2018-03-01arm/translate-a64: implement simd_scalar_three_reg_same_fp16Alex Bennée
2018-03-01arm/translate-a64: add all FP16 ops in simd_scalar_pairwiseAlex Bennée
2018-03-01arm/translate-a64: add FP16 FMOV to simd_mod_immAlex Bennée
2018-03-01arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16Alex Bennée
2018-03-01arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16Alex Bennée
2018-03-01arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16Alex Bennée
2018-03-01arm/translate-a64: add FP16 FRECPEAlex Bennée
2018-03-01arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16Alex Bennée
2018-03-01arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16Alex Bennée
2018-03-01arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16Alex Bennée
2018-03-01arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16Alex Bennée
2018-03-01arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16Alex Bennée
2018-03-01arm/translate-a64: initial decode for simd_two_reg_misc_fp16Alex Bennée
2018-03-01arm/translate-a64: add FP16 x2 ops for simd_indexedAlex Bennée
2018-03-01arm/translate-a64: add FP16 FMULX/MLS/FMLA to simd_indexedAlex Bennée
2018-03-01arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16Alex Bennée
2018-03-01arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16Alex Bennée
2018-03-01arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16Alex Bennée
2018-03-01arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16Alex Bennée
2018-03-01arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16Alex Bennée
2018-03-01arm/translate-a64: initial decode for simd_three_reg_same_fp16Alex Bennée
2018-03-01arm/translate-a64: handle_3same_64 comment fixAlex Bennée
2018-03-01arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV)Alex Bennée
2018-03-01target/arm/helper: pass explicit fpst to set_rmodeAlex Bennée
2018-03-01target/arm/cpu.h: add additional float_status flagsAlex Bennée
2018-02-15target/arm: Handle SVE registers when using clear_vec_highRichard Henderson
2018-02-15target/arm: Enforce access to ZCR_EL at translationRichard Henderson
2018-02-15target/arm: Enforce FP access to FPCR/FPSRRichard Henderson
2018-02-09target/arm: Add SVE state to TB->FLAGSRichard Henderson
2018-02-09target/arm: Expand vector registers for SVERichard Henderson
2018-02-09target/arm: implement SM4 instructionsArd Biesheuvel
2018-02-09target/arm: implement SM3 instructionsArd Biesheuvel
2018-02-09target/arm: implement SHA-3 instructionsArd Biesheuvel
2018-02-09target/arm: implement SHA-512 instructionsArd Biesheuvel
2018-02-08target/arm: Use vector infrastructure for aa64 orr/bic immediateRichard Henderson
2018-02-08target/arm: Use vector infrastructure for aa64 multipliesRichard Henderson
2018-02-08target/arm: Use vector infrastructure for aa64 comparesRichard Henderson
2018-02-08target/arm: Use vector infrastructure for aa64 constant shiftsRichard Henderson
2018-02-08target/arm: Use vector infrastructure for aa64 dup/moviRichard Henderson
2018-02-08target/arm: Use vector infrastructure for aa64 mov/not/negRichard Henderson
2018-02-08target/arm: Use vector infrastructure for aa64 add/sub/logicRichard Henderson
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