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path: root/target/arm/tcg
AgeCommit message (Expand)Author
2023-07-31target/arm/tcg: Don't build AArch64 decodetree files for qemu-system-armPeter Maydell
2023-07-31target/arm: Avoid writing to constant TCGv in trans_CSEL()Peter Maydell
2023-07-31target/arm: Fix MemOp for STGPRichard Henderson
2023-07-25arm: spelling fixesMichael Tokarev
2023-07-09target/arm: Use aesdec_IMCRichard Henderson
2023-07-09target/arm: Use aesenc_MCRichard Henderson
2023-07-09target/arm: Use aesdec_ISB_ISR_AKRichard Henderson
2023-07-09target/arm: Use aesenc_SB_SR_AKRichard Henderson
2023-07-08target/arm: Demultiplex AESE and AESMCRichard Henderson
2023-07-08target/arm: Move aesmc and aesimc tables to crypto/aes.cRichard Henderson
2023-07-06target/arm: Define neoverse-v1Peter Maydell
2023-07-06target/arm: Fix SME full tile indexingRichard Henderson
2023-07-03plugins: force slow path when plugins instrument memory opsAlex Bennée
2023-06-23target/arm: Fix sve predicate store, 8 <= VQ <= 15Richard Henderson
2023-06-23target/arm: Add cpu properties for enabling FEAT_RMERichard Henderson
2023-06-23target/arm: Implement GPC exceptionsRichard Henderson
2023-06-20meson: Replace softmmu_ss -> system_ssPhilippe Mathieu-Daudé
2023-06-19target/arm: Convert load/store tags insns to decodetreePeter Maydell
2023-06-19target/arm: Convert load/store single structure to decodetreePeter Maydell
2023-06-19target/arm: Convert load/store (multiple structures) to decodetreePeter Maydell
2023-06-19target/arm: Convert LDAPR/STLR (imm) to decodetreePeter Maydell
2023-06-19target/arm: Convert load (pointer auth) insns to decodetreePeter Maydell
2023-06-19target/arm: Convert atomic memory ops to decodetreePeter Maydell
2023-06-19target/arm: Convert LDR/STR reg+reg to decodetreePeter Maydell
2023-06-19target/arm: Convert LDR/STR with 12-bit immediate to decodetreePeter Maydell
2023-06-19target/arm: Convert ld/st reg+imm9 insns to decodetreePeter Maydell
2023-06-19target/arm: Convert load/store-pair to decodetreePeter Maydell
2023-06-19target/arm: Convert load reg (literal) group to decodetreePeter Maydell
2023-06-19target/arm: Convert LDXP, STXP, CASP, CAS to decodetreePeter Maydell
2023-06-19target/arm: Convert load/store exclusive and ordered to decodetreePeter Maydell
2023-06-19target/arm: Convert exception generation instructions to decodetreePeter Maydell
2023-06-19target/arm: Convert MSR (reg), MRS, SYS, SYSL to decodetreePeter Maydell
2023-06-19target/arm: Convert MSR (immediate) to decodetreePeter Maydell
2023-06-19target/arm: Convert CFINV, XAFLAG and AXFLAG to decodetreePeter Maydell
2023-06-19target/arm: Convert barrier insns to decodetreePeter Maydell
2023-06-19target/arm: Convert hint instruction space to decodetreePeter Maydell
2023-06-19target/arm: Consistently use finalize_memop_asimd() for ASIMD loads/storesPeter Maydell
2023-06-19target/arm: Pass memop to gen_mte_check1_mmuidx() in reg_imm9 decodePeter Maydell
2023-06-19target/arm: Return correct result for LDG when ATA=0Peter Maydell
2023-06-19target/arm: Fix return value from LDSMIN/LDSMAX 8/16 bit atomicsPeter Maydell
2023-06-06target/arm: Enable FEAT_LSE2 for -cpu maxRichard Henderson
2023-06-06target/arm: Move mte check for store-exclusiveRichard Henderson
2023-06-06target/arm: Relax ordered/atomic alignment checks for LSE2Richard Henderson
2023-06-06target/arm: Add SCTLR.nAA to TBFLAG_A64Richard Henderson
2023-06-06target/arm: Check alignment in helper_mte_checkRichard Henderson
2023-06-06target/arm: Pass single_memop to gen_mte_checkNRichard Henderson
2023-06-06target/arm: Pass memop to gen_mte_check1*Richard Henderson
2023-06-06target/arm: Hoist finalize_memop out of do_fp_{ld, st}Richard Henderson
2023-06-06target/arm: Hoist finalize_memop out of do_gpr_{ld, st}Richard Henderson
2023-06-06target/arm: Load/store integer pair with one tcg operationRichard Henderson