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path: root/target/arm/cpu.h
AgeCommit message (Expand)Author
2021-05-25target/arm: Implement aarch64 SUDOT, USDOTRichard Henderson
2021-05-25target/arm: Implement SVE2 crypto constructive binary operationsRichard Henderson
2021-05-25target/arm: Implement SVE2 crypto destructive binary operationsRichard Henderson
2021-05-25target/arm: Implement SVE mixed sign dot product (indexed)Richard Henderson
2021-05-25target/arm: Implement SVE2 FMMLAStephen Long
2021-05-25target/arm: Implement SVE2 bitwise permuteRichard Henderson
2021-05-25target/arm: Implement SVE2 PMULLB, PMULLTRichard Henderson
2021-05-25target/arm: Add ID_AA64ZFR0 fields and isar_feature_aa64_sve2Richard Henderson
2021-05-25target/arm: Add support for FEAT_TLBIOSRebecca Cran
2021-05-25target/arm: Add support for FEAT_TLBIRANGERebecca Cran
2021-04-30target/arm: Add ALIGN_MEM to TBFLAG_ANYRichard Henderson
2021-04-30target/arm: Move TBFLAG_ANY bits to the bottomRichard Henderson
2021-04-30target/arm: Move TBFLAG_AM32 bits to the topRichard Henderson
2021-04-30target/arm: Move mode specific TB flags to tb->cs_baseRichard Henderson
2021-04-30target/arm: Introduce CPUARMTBFlagsRichard Henderson
2021-04-30target/arm: Add wrapper macros for accessing tbflagsRichard Henderson
2021-04-30target/arm: Rename TBFLAG_ANY, PSTATE_SSRichard Henderson
2021-04-30target/arm: Rename TBFLAG_A32, SCTLR_BRichard Henderson
2021-04-06Revert "target/arm: Make number of counters in PMCR follow the CPU"Peter Maydell
2021-03-30target/arm: Make number of counters in PMCR follow the CPUPeter Maydell
2021-03-05target/arm: Add support for FEAT_SSBS, Speculative Store Bypass SafeRebecca Cran
2021-02-16linux-user/aarch64: Implement PROT_MTERichard Henderson
2021-02-16linux-user/aarch64: Implement PR_TAGGED_ADDR_ENABLERichard Henderson
2021-02-11target/arm: Add support for FEAT_DIT, Data Independent TimingRebecca Cran
2021-02-11target/arm: Fix SCR RES1 handlingMike Nawrocki
2021-01-29target/arm: Implement ID_PFR2Richard Henderson
2021-01-19target/arm: Implement SCR_EL2.EEL2Rémi Denis-Courmont
2021-01-19target/arm: set HPFAR_EL2.NS on secure stage 2 faultsRémi Denis-Courmont
2021-01-19target/arm: secure stage 2 translation regimeRémi Denis-Courmont
2021-01-19target/arm: add ARMv8.4-SEL2 system registersRémi Denis-Courmont
2021-01-19target/arm: add MMU stage 1 for Secure EL2Rémi Denis-Courmont
2021-01-19target/arm: Define isar_feature function to test for presence of SEL2Rémi Denis-Courmont
2021-01-19target/arm: use arm_is_el2_enabled() where applicableRémi Denis-Courmont
2021-01-19target/arm: add arm_is_el2_enabled() helperRémi Denis-Courmont
2021-01-19target/arm: Add cpu properties to control pauthRichard Henderson
2021-01-19target/arm: Implement an IMPDEF pauth algorithmRichard Henderson
2021-01-18semihosting: Change common-semi API to be architecture-independentKeith Packard
2021-01-12target/arm: add aarch32 ID register fields to cpu.hLeif Lindholm
2021-01-12target/arm: add aarch64 ID register fields to cpu.hLeif Lindholm
2021-01-12target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.hLeif Lindholm
2021-01-12target/arm: make ARMCPU.ctr 64-bitLeif Lindholm
2021-01-12target/arm: make ARMCPU.clidr 64-bitLeif Lindholm
2021-01-12target/arm: fix typo in cpu.h ID_AA64PFR1 field nameLeif Lindholm
2021-01-12target/arm: ARMv8.4-TTST extensionRémi Denis-Courmont
2020-12-10target/arm: Implement M-profile "minimal RAS implementation"Peter Maydell
2020-12-10hw/intc/armv7m_nvic: Support v8.1M CCR.TRD bitPeter Maydell
2020-12-10hw/intc/armv7m_nvic: Update FPDSCR masking for v8.1MPeter Maydell
2020-12-10target/arm: Implement M-profile FPSCR_nzcvqcPeter Maydell
2020-12-10target/arm: Refactor M-profile VMSR/VMRS handlingPeter Maydell
2020-12-10target/arm: Implement VSCCLRM insnPeter Maydell