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path: root/target/arm/cpu.h
AgeCommit message (Expand)Author
2018-03-09target/arm: Add a core count propertyAlistair Francis
2018-03-02target/arm: Add ARM_FEATURE_V8_FCMARichard Henderson
2018-03-02target/arm: Add ARM_FEATURE_V8_RDMRichard Henderson
2018-03-02target/arm: Define init-svtor property for the reset secure VTOR valuePeter Maydell
2018-03-02target/arm: Define an IDAU interfacePeter Maydell
2018-03-01target/arm/cpu.h: add additional float_status flagsAlex Bennée
2018-03-01target/arm/cpu.h: update comment for half-precision valuesAlex Bennée
2018-03-01target/arm/cpu64: introduce ARM_V8_FP16 feature bitAlex Bennée
2018-02-21target/*/cpu.h: remove softfloat.hAlex Bennée
2018-02-15target/arm: Implement v8M MSPLIM and PSPLIM registersPeter Maydell
2018-02-15hw/intc/armv7m_nvic: Implement SCRPeter Maydell
2018-02-15hw/intc/armv7m_nvic: Implement cache ID registersPeter Maydell
2018-02-15target/arm: Enforce access to ZCR_EL at translationRichard Henderson
2018-02-15target/arm: Enforce FP access to FPCR/FPSRRichard Henderson
2018-02-09target/arm: Add SVE state to TB->FLAGSRichard Henderson
2018-02-09target/arm: Add ZCR_ELxRichard Henderson
2018-02-09target/arm: Add predicate registers for SVERichard Henderson
2018-02-09target/arm: Expand vector registers for SVERichard Henderson
2018-02-09target/arm: implement SM4 instructionsArd Biesheuvel
2018-02-09target/arm: implement SM3 instructionsArd Biesheuvel
2018-02-09target/arm: implement SHA-3 instructionsArd Biesheuvel
2018-02-09target/arm: implement SHA-512 instructionsArd Biesheuvel
2018-02-09target/arm: Split "get pending exception info" from "acknowledge it"Peter Maydell
2018-02-09target/arm: Add armv7m_nvic_set_pending_derived()Peter Maydell
2018-02-08target/arm: Align vector registersRichard Henderson
2018-01-25target/arm: Move cpu_get_tb_cpu_state out of lineRichard Henderson
2018-01-25target/arm: Add ARM_FEATURE_SVERichard Henderson
2018-01-25target/arm: Add aa{32, 64}_vfp_{dreg, qreg} helpersRichard Henderson
2018-01-25target/arm: Change the type of vfp.regsRichard Henderson
2017-12-13target/arm: Create new arm_v7m_mmu_idx_for_secstate_and_priv()Peter Maydell
2017-12-13target/arm: Split M profile MNegPri mmu index into user and privPeter Maydell
2017-10-06target/arm: Factor out "get mmuidx for specified security state"Peter Maydell
2017-10-06target/arm: Fix calculation of secure mm_idx valuesPeter Maydell
2017-10-06nvic: Implement Security Attribution Unit registersPeter Maydell
2017-10-06target/arm: Add new-in-v8M SFSR and SFARPeter Maydell
2017-10-06target/arm: Prepare for CONTROL.SPSEL being nonzero in Handler modePeter Maydell
2017-09-21nvic: Support banked exceptions in acknowledge and completePeter Maydell
2017-09-21target/arm: Handle banking in negative-execution-priority check in cpu_mmu_in...Peter Maydell
2017-09-21nvic: Make set_pending and clear_pending take a secure parameterPeter Maydell
2017-09-21nvic: Implement AIRCR changes for v8MPeter Maydell
2017-09-19arm: drop intermediate cpu_model -> cpu type parsing and use cpu type directlyIgor Mammedov
2017-09-14target/arm: Use M_REG_NUM_BANKS rather than hardcoding 2Peter Maydell
2017-09-07target/arm: Add Jazelle featurePortia Stephens
2017-09-07target/arm: Implement BXNS, and banked stack pointersPeter Maydell
2017-09-07target/arm: Make CFSR register banked for v8MPeter Maydell
2017-09-07target/arm: Make MMFAR banked for v8MPeter Maydell
2017-09-07target/arm: Make CCR register banked for v8MPeter Maydell
2017-09-07target/arm: Make MPU_CTRL register banked for v8MPeter Maydell
2017-09-07target/arm: Make MPU_RNR register banked for v8MPeter Maydell
2017-09-07target/arm: Make MPU_RBAR, MPU_RLAR banked for v8MPeter Maydell