Age | Commit message (Expand) | Author |
2018-06-22 | target/arm: Introduce ARM_FEATURE_M_MAIN | Julia Suvorova |
2018-05-18 | target/arm: Implement SVE Predicate Misc Group | Richard Henderson |
2018-05-18 | target/arm: Implement SVE Predicate Logical Operations Group | Richard Henderson |
2018-05-18 | target/arm: Add the XML dynamic generation | Abdallah Bouassida |
2018-05-18 | target/arm: Add "ARM_CP_NO_GDB" as a new bit field for ARMCPRegInfo type | Abdallah Bouassida |
2018-05-10 | target/arm: Introduce ARM_FEATURE_V8_ATOMICS and initial decode | Richard Henderson |
2018-04-26 | target/arm: Make PMOVSCLR and PMUSERENR 64 bits wide | Aaron Lindsay |
2018-04-26 | target/arm: Add pre-EL change hooks | Aaron Lindsay |
2018-04-26 | target/arm: Support multiple EL change hooks | Aaron Lindsay |
2018-04-26 | target/arm: Fetch GICv3 state directly from CPUARMState | Aaron Lindsay |
2018-03-19 | cpu: get rid of unused cpu_init() defines | Igor Mammedov |
2018-03-19 | cpu: add CPU_RESOLVING_TYPE macro | Igor Mammedov |
2018-03-09 | target/arm: Query host CPU features on-demand at instance init | Peter Maydell |
2018-03-09 | linux-user: Implement aarch64 PR_SVE_SET/GET_VL | Richard Henderson |
2018-03-09 | target/arm: Add a core count property | Alistair Francis |
2018-03-02 | target/arm: Add ARM_FEATURE_V8_FCMA | Richard Henderson |
2018-03-02 | target/arm: Add ARM_FEATURE_V8_RDM | Richard Henderson |
2018-03-02 | target/arm: Define init-svtor property for the reset secure VTOR value | Peter Maydell |
2018-03-02 | target/arm: Define an IDAU interface | Peter Maydell |
2018-03-01 | target/arm/cpu.h: add additional float_status flags | Alex Bennée |
2018-03-01 | target/arm/cpu.h: update comment for half-precision values | Alex Bennée |
2018-03-01 | target/arm/cpu64: introduce ARM_V8_FP16 feature bit | Alex Bennée |
2018-02-21 | target/*/cpu.h: remove softfloat.h | Alex Bennée |
2018-02-15 | target/arm: Implement v8M MSPLIM and PSPLIM registers | Peter Maydell |
2018-02-15 | hw/intc/armv7m_nvic: Implement SCR | Peter Maydell |
2018-02-15 | hw/intc/armv7m_nvic: Implement cache ID registers | Peter Maydell |
2018-02-15 | target/arm: Enforce access to ZCR_EL at translation | Richard Henderson |
2018-02-15 | target/arm: Enforce FP access to FPCR/FPSR | Richard Henderson |
2018-02-09 | target/arm: Add SVE state to TB->FLAGS | Richard Henderson |
2018-02-09 | target/arm: Add ZCR_ELx | Richard Henderson |
2018-02-09 | target/arm: Add predicate registers for SVE | Richard Henderson |
2018-02-09 | target/arm: Expand vector registers for SVE | Richard Henderson |
2018-02-09 | target/arm: implement SM4 instructions | Ard Biesheuvel |
2018-02-09 | target/arm: implement SM3 instructions | Ard Biesheuvel |
2018-02-09 | target/arm: implement SHA-3 instructions | Ard Biesheuvel |
2018-02-09 | target/arm: implement SHA-512 instructions | Ard Biesheuvel |
2018-02-09 | target/arm: Split "get pending exception info" from "acknowledge it" | Peter Maydell |
2018-02-09 | target/arm: Add armv7m_nvic_set_pending_derived() | Peter Maydell |
2018-02-08 | target/arm: Align vector registers | Richard Henderson |
2018-01-25 | target/arm: Move cpu_get_tb_cpu_state out of line | Richard Henderson |
2018-01-25 | target/arm: Add ARM_FEATURE_SVE | Richard Henderson |
2018-01-25 | target/arm: Add aa{32, 64}_vfp_{dreg, qreg} helpers | Richard Henderson |
2018-01-25 | target/arm: Change the type of vfp.regs | Richard Henderson |
2017-12-13 | target/arm: Create new arm_v7m_mmu_idx_for_secstate_and_priv() | Peter Maydell |
2017-12-13 | target/arm: Split M profile MNegPri mmu index into user and priv | Peter Maydell |
2017-10-06 | target/arm: Factor out "get mmuidx for specified security state" | Peter Maydell |
2017-10-06 | target/arm: Fix calculation of secure mm_idx values | Peter Maydell |
2017-10-06 | nvic: Implement Security Attribution Unit registers | Peter Maydell |
2017-10-06 | target/arm: Add new-in-v8M SFSR and SFAR | Peter Maydell |
2017-10-06 | target/arm: Prepare for CONTROL.SPSEL being nonzero in Handler mode | Peter Maydell |