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path: root/target/arm/cpu.c
AgeCommit message (Expand)Author
2020-07-20hw/arm/virt: Enable MTE via a machine propertyRichard Henderson
2020-06-26target/arm: Create tagged ram when MTE is enabledRichard Henderson
2020-06-26target/arm: Complete TBI clearing for user-only for SVERichard Henderson
2020-06-26target/arm: Restrict the values of DCZID.BS under TCGRichard Henderson
2020-06-26target/arm: Define arm_cpu_do_unaligned_access for user-onlyRichard Henderson
2020-06-23target/arm: Check supported KVM features globally (not per vCPU)Philippe Mathieu-Daudé
2020-06-16target/arm/cpu: adjust virtual time for all KVM arm cpusfangying
2020-05-15qom: Drop parameter @errp of object_property_add() & friendsMarkus Armbruster
2020-05-11target/arm: Restrict TCG cpus to TCG accelPhilippe Mathieu-Daudé
2020-05-11target/arm/cpu: Restrict v8M IDAU interface to Aarch32 CPUsPhilippe Mathieu-Daudé
2020-05-11target/arm/cpu: Use ARRAY_SIZE() to iterate over ARMCPUInfo[]Philippe Mathieu-Daudé
2020-05-11target/arm: Make set_feature() available for other filesThomas Huth
2020-05-04target/arm: Use uint64_t for midr field in CPU state structPhilippe Mathieu-Daudé
2020-05-04target/arm: Implement ARMv8.2-TTS2UXNPeter Maydell
2020-04-30target/arm/cpu: Update coding style to make checkpatch.pl happyPhilippe Mathieu-Daudé
2020-04-30target/arm: Make cpu_register() available for other filesThomas Huth
2020-03-19Merge remote-tracking branch 'remotes/ehabkost/tags/x86-and-machine-pull-requ...Peter Maydell
2020-03-18Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-and-gdbstub-1...Peter Maydell
2020-03-17cpu: Use DeviceClass reset instead of a special CPUClass resetPeter Maydell
2020-03-17target/arm: default SVE length to 64 bytes for linux-userAlex Bennée
2020-03-16qom/object: Use common get/set uint helpersFelipe Franciosi
2020-03-05target/arm: Remove EL2 and EL3 setup from user-onlyRichard Henderson
2020-03-05target/arm: Disable has_el2 and has_el3 for user-onlyRichard Henderson
2020-03-05target/arm: Implement (trivially) ARMv8.2-TTCNPPeter Maydell
2020-02-28target/arm: Remove ARM_FEATURE_VFP*Richard Henderson
2020-02-28target/arm: Replace ARM_FEATURE_VFP4 with isar_feature_aa32_simdfmacRichard Henderson
2020-02-28target/arm: Add isar_feature_aa64_fp_simd, isar_feature_aa32_vfpRichard Henderson
2020-02-28target/arm: Add isar_feature_aa32_vfp_simdRichard Henderson
2020-02-21target/arm: Set MVFR0.FPSP for ARMv5 cpusRichard Henderson
2020-02-21target/arm: Use isar_feature_aa32_simd_r32 more placesRichard Henderson
2020-02-21target/arm: Correctly implement ACTLR2, HACTLR2Peter Maydell
2020-02-21target/arm: Test correct register in aa32_pan and aa32_ats1e1 checksPeter Maydell
2020-02-21target/arm: Move DBGDIDR into ARMISARegistersPeter Maydell
2020-02-21target/arm: Add _aa64_ and _any_ versions of pmu_8_1 isar checksPeter Maydell
2020-02-21target/arm: Define an aa32_pmu_8_1 isar feature test functionPeter Maydell
2020-02-21target/arm: Use FIELD macros for clearing ID_DFR0 PERFMON fieldPeter Maydell
2020-02-21target/arm: Add and use FIELD definitions for ID_AA64DFR0_EL1Peter Maydell
2020-02-21target/arm: Add _aa32_ to isar_feature functions testing 32-bit ID registersPeter Maydell
2020-02-13target/arm: Enable ARMv8.2-ATS1E1 in -cpu maxRichard Henderson
2020-02-07target/arm: Raise only one interrupt in arm_cpu_exec_interruptRichard Henderson
2020-02-07target/arm: Use bool for unmasked in arm_excp_unmaskedRichard Henderson
2020-02-07target/arm: Pass more cpu state to arm_excp_unmaskedRichard Henderson
2020-02-07target/arm: Move arm_excp_unmasked to cpu.cRichard Henderson
2020-02-07target/arm: Add the hypervisor virtual counterRichard Henderson
2020-01-30target/arm/cpu: Add the kvm-no-adjvtime CPU propertyAndrew Jones
2020-01-27Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell
2020-01-24qdev: set properties with device_class_set_props()Marc-André Lureau
2020-01-24qdev: remove extraneous errorMarc-André Lureau
2020-01-24cpu: Use cpu_class_set_parent_reset()Greg Kurz
2020-01-23target/arm: add PMU feature to cortex-r5 and cortex-r5fClement Deschamps