Age | Commit message (Expand) | Author |
2013-11-08 | target-xtensa: add missing DEBUG section to dc233c config | Max Filippov |
2013-10-15 | target-xtensa: add in_asm logging | Max Filippov |
2013-10-10 | tcg: Move helper registration into tcg_context_init | Richard Henderson |
2013-09-02 | target: Include softmmu_exec.h where forgotten | Richard Henderson |
2013-09-02 | tcg: Change tcg_gen_exit_tb argument to uintptr_t | Richard Henderson |
2013-08-22 | aio / timers: Switch entire codebase to the new timer API | Alex Bligh |
2013-08-05 | Merge remote-tracking branch 'filippov/tags/20130729-xtensa' into staging | Anthony Liguori |
2013-07-29 | target-xtensa: check register window inline | Max Filippov |
2013-07-29 | target-xtensa: don't generate dead code to access invalid SRs | Max Filippov |
2013-07-29 | target-xtensa: avoid double-stopping at breakpoints | Max Filippov |
2013-07-29 | target-xtensa: add fallthrough markers | Max Filippov |
2013-07-29 | cpu: Partially revert "cpu: Change qemu_init_vcpu() argument to CPUState" | Andreas Färber |
2013-07-27 | cpu: Introduce CPUClass::gdb_{read,write}_register() | Andreas Färber |
2013-07-27 | gdbstub: Replace GET_REG*() macros with gdb_get_reg*() functions | Andreas Färber |
2013-07-27 | target-xtensa: Move cpu_gdb_{read,write}_register() | Andreas Färber |
2013-07-26 | cpu: Introduce CPUState::gdb_num_regs and CPUClass::gdb_num_core_regs | Andreas Färber |
2013-07-26 | target-xtensa: Introduce XtensaCPU subclasses | Andreas Färber |
2013-07-23 | exec: Change cpu_memory_rw_debug() argument to CPUState | Andreas Färber |
2013-07-23 | cpu: Turn cpu_get_phys_page_debug() into a CPUClass hook | Andreas Färber |
2013-07-23 | cpu: Move singlestep_enabled field from CPU_COMMON to CPUState | Andreas Färber |
2013-07-23 | cpu: Introduce CPUClass::synchronize_from_tb() for cpu_pc_from_tb() | Andreas Färber |
2013-07-23 | cpu: Introduce CPUClass::set_pc() for gdb_set_cpu_pc() | Andreas Färber |
2013-07-09 | target-xtensa: Change gen_intermediate_code_internal() arg to XtensaCPU | Andreas Färber |
2013-07-09 | target-xtensa: gen_intermediate_code_internal() should be inlined | Andreas Färber |
2013-07-09 | cpu: Drop unnecessary dynamic casts in *_env_get_cpu() | Andreas Färber |
2013-06-28 | cpu: Change qemu_init_vcpu() argument to CPUState | Andreas Färber |
2013-06-28 | cpu: Turn cpu_dump_{state,statistics}() into CPUState hooks | Andreas Färber |
2013-03-12 | cpu: Replace do_interrupt() by CPUClass::do_interrupt method | Andreas Färber |
2013-03-12 | cpu: Move halted and interrupt_request fields to CPUState | Andreas Färber |
2013-03-03 | gen-icount.h: Rename gen_icount_start/end to gen_tb_start/end | Peter Maydell |
2013-03-03 | cpu: Introduce ENV_OFFSET macros | Andreas Färber |
2013-02-23 | target-xtensa: Use add2/sub2 for mac | Richard Henderson |
2013-02-23 | target-xtensa: Use mul*2 for mul*hi | Richard Henderson |
2013-02-16 | cpu: Add CPUArchState pointer to CPUState | Andreas Färber |
2013-02-16 | target-xtensa: Move TCG initialization to XtensaCPU initfn | Andreas Färber |
2013-02-16 | target-xtensa: Introduce QOM realizefn for XtensaCPU | Andreas Färber |
2013-02-01 | target-xtensa: Mark as unmigratable | Andreas Färber |
2012-12-22 | target-xtensa: fix search_pc for the last TB opcode | Max Filippov |
2012-12-19 | softmmu: move include files to include/sysemu/ | Paolo Bonzini |
2012-12-19 | misc: move include files to include/qemu/ | Paolo Bonzini |
2012-12-19 | qom: move include files to include/qom/ | Paolo Bonzini |
2012-12-19 | exec: move include files to include/exec/ | Paolo Bonzini |
2012-12-19 | build: kill libdis, move disassemblers to disas/ | Paolo Bonzini |
2012-12-16 | exec: refactor cpu_restore_state | Blue Swirl |
2012-12-15 | target-xtensa: fix ITLB/DTLB page protection flags | Max Filippov |
2012-12-08 | target-xtensa: use movcond where possible | Max Filippov |
2012-12-08 | target-xtensa: implement MISC SR | Max Filippov |
2012-12-08 | target-xtensa: better control rsr/wsr/xsr access to SRs | Max Filippov |
2012-12-08 | target-xtensa: restrict available SRs by enabled options | Max Filippov |
2012-12-08 | target-xtensa: implement CACHEATTR SR | Max Filippov |