Age | Commit message (Expand) | Author |
2011-11-02 | target-xtensa: raise an exception for invalid and reserved opcodes | Max Filippov |
2011-11-02 | target-xtensa: handle cache options in the overlay tool | Max Filippov |
2011-11-02 | target-xtensa: mask out undefined bits of WINDOWSTART SR | Max Filippov |
2011-10-16 | target-xtensa: add fsf core | Max Filippov |
2011-10-16 | target-xtensa: add dc232b core | Max Filippov |
2011-10-16 | target-xtensa: extract core configuration from overlay | Max Filippov |
2011-10-16 | target-xtensa: implement external interrupt mapping | Max Filippov |
2011-10-16 | target-xtensa: remove hand-written xtensa cores implementations | Max Filippov |
2011-10-16 | target-xtensa: increase xtensa options accuracy | Max Filippov |
2011-10-15 | target-xtensa: implement MAC16 option | Max Filippov |
2011-10-15 | target-xtensa: fix guest hang on masked CCOMPARE interrupt | Max Filippov |
2011-10-01 | softmmu_header: pass CPUState to tlb_fill | Blue Swirl |
2011-09-10 | target-xtensa: add dc232b core and board | Max Filippov |
2011-09-10 | target-xtensa: implement boolean option | Max Filippov |
2011-09-10 | target-xtensa: implement memory protection options | Max Filippov |
2011-09-10 | target-xtensa: add gdb support | Max Filippov |
2011-09-10 | target-xtensa: implement relocatable vectors | Max Filippov |
2011-09-10 | target-xtensa: implement CPENABLE and PRID SRs | Max Filippov |
2011-09-10 | target-xtensa: implement accurate window check | Max Filippov |
2011-09-10 | target-xtensa: implement interrupt option | Max Filippov |
2011-09-10 | target-xtensa: implement SIMCALL | Max Filippov |
2011-09-10 | target-xtensa: implement unaligned exception option | Max Filippov |
2011-09-10 | target-xtensa: implement extended L32R | Max Filippov |
2011-09-10 | target-xtensa: implement loop option | Max Filippov |
2011-09-10 | target-xtensa: implement windowed registers | Max Filippov |
2011-09-10 | target-xtensa: implement RST2 group (32 bit mul/div/rem) | Max Filippov |
2011-09-10 | target-xtensa: implement exceptions | Max Filippov |
2011-09-10 | target-xtensa: add PS register and access control | Max Filippov |
2011-09-10 | target-xtensa: implement CACHE group | Max Filippov |
2011-09-10 | target-xtensa: implement SYNC group | Max Filippov |
2011-09-10 | target-xtensa: mark reserved and TBD opcodes | Max Filippov |
2011-09-10 | target-xtensa: implement LSAI group | Max Filippov |
2011-09-10 | target-xtensa: implement shifts (ST1 and RST1 groups) | Max Filippov |
2011-09-10 | target-xtensa: implement RST3 group | Max Filippov |
2011-09-10 | target-xtensa: add special and user registers | Max Filippov |
2011-09-10 | target-xtensa: implement JX/RET0/CALLX | Max Filippov |
2011-09-10 | target-xtensa: implement conditional jumps | Max Filippov |
2011-09-10 | target-xtensa: implement RT0 group | Max Filippov |
2011-09-10 | target-xtensa: implement narrow instructions | Max Filippov |
2011-09-10 | target-xtensa: implement disas_xtensa_insn | Max Filippov |
2011-09-10 | target-xtensa: add target stubs | Max Filippov |