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2012-03-03Merge branch 'upstream' of git://qemu.weilnetz.de/qemuBlue Swirl
* 'upstream' of git://qemu.weilnetz.de/qemu: Move definition of HOST_LONG_BITS to qemu-common.h target-xtensa: Clean includes target-unicore32: Clean includes target-sh4: Clean includes target-s390x: Clean includes target-ppc: Clean includes target-mips: Clean includes target-microblaze: Clean includes target-m68k: Clean includes target-lm32: Clean includes target-i386: Clean includes target-cris: Clean includes target-arm: Clean includes target-alpha: Clean includes Remove macro HOST_LONG_SIZE
2012-02-28target-xtensa: Clean includesStefan Weil
Remove some include statements which are not needed. Acked-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Stefan Weil <sw@weilnetz.de>
2012-02-20target-xtensa: add DEBUG_SECTION to overlay toolMax Filippov
Fill debug configuration from overlay definitions in the DEBUG_SECTION. Add DEBUG_SECTION to DC232B and FSF cores. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2012-02-20target-xtensa: add DBREAK data breakpointsMax Filippov
Add DBREAKA/DBREAKC SRs and implement DBREAK breakpoints as debug watchpoints. This implementation is not fully compliant to ISA: when a breakpoint is set to an unmapped/inaccessible memory address it generates TLB/memory protection exception instead of debug exception. See ISA, 4.7.7.3, 4.7.7.6 for more details. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2012-02-18target-xtensa: add ICOUNT SR and debug exceptionMax Filippov
ICOUNT SR gets incremented on every instruction completion provided that CINTLEVEL at the beginning of the instruction execution is lower than ICOUNTLEVEL. When ICOUNT would increment to 0 a debug exception is raised if CINTLEVEL is lower than DEBUGLEVEL. See ISA, 4.7.7.5 for more details. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2012-02-18target-xtensa: implement instruction breakpointsMax Filippov
Add IBREAKA/IBREAKENABLE SRs and implement debug exception, BREAK and BREAK.N instructions and IBREAK breakpoints. IBREAK breakpoint address is considered constant for TB lifetime. On IBREAKA/IBREAKENABLE change corresponding TBs are invalidated. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2012-02-18target-xtensa: add DEBUGCAUSE SR and configurationMax Filippov
DEBUGCAUSE SR holds information about the most recent debug exception. See ISA, 4.7.7 for more details. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2012-02-18target-xtensa: fetch 3rd opcode byte only when neededMax Filippov
According to ISA, 3.5.4, third opcode byte should not be fetched for 2-byte instructions. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2012-02-18target-xtensa: implement info tlb monitor commandMax Filippov
Command dumps valid ITLB and DTLB entries. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2012-02-18target-xtensa: define TLB_TEMPLATE for MMU-less coresMax Filippov
TLB_TEMPLATE macro specifies TLB geometry in the core configuration. Make TLB_TEMPLATE available for region protection core variants, defining 1 way ITLB and DTLB with 8 entries each. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2011-11-26target-xtensa: fix MMUv3 initializationMax Filippov
- ITLB/DTLB ways 5 and 6 have 4 and 8 entries respectively; - ITLB/DTLB way 6 attr field is set to 3 on reset. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-11-02target-xtensa: raise an exception for invalid and reserved opcodesMax Filippov
This includes opcodes from disabled features and those marked reserved in the ISA. Also end TB on opcodes that definitely generate an exception: illegal instructions, syscall and privileged instructions. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2011-11-02target-xtensa: handle cache options in the overlay toolMax Filippov
Cache options must be enabled for the cores that have cache to avoid illegal instruction exceptions. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2011-11-02target-xtensa: mask out undefined bits of WINDOWSTART SRMax Filippov
According to ISA, table 5-156, bits 32:NAREG/4 of the WINDOWSTART SR must be zero. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2011-10-16target-xtensa: add fsf coreMax Filippov
This is FSF big endian core implemented through linux overlay. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-16target-xtensa: add dc232b coreMax Filippov
This is Diamond 232L Standard Core Rev.B (LE), implemented through linux/gdb overlay. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-16target-xtensa: extract core configuration from overlayMax Filippov
Introduce overlay_tool.h that defines core configuration blocks from data available in the linux architecture variant overlay. Overlay data is automatically generated in the core configuration process by Tensilica tools and can be directly converted to qemu xtensa core description by overlay_tool.h Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-16target-xtensa: implement external interrupt mappingMax Filippov
Xtensa cores may have different mapping of external interrupt pins to internal IRQ numers. Implement API to acquire core IRQ by its external interrupt number. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-16target-xtensa: remove hand-written xtensa cores implementationsMax Filippov
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-16target-xtensa: increase xtensa options accuracyMax Filippov
- add separate options for each operation in the MISC_OP; - add an option for MULSH/MULUH; - put S32C1I under conditional store option. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-15target-xtensa: implement MAC16 optionMax Filippov
See ISA, 4.3.7 for the details. - add ACC and MR special registers; - implement MAC16 and all inner MAC* opcode groups. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-15target-xtensa: fix guest hang on masked CCOMPARE interruptMax Filippov
QEMU timer is used to post CCOMPARE interrupt when the core is halted. If that CCOMPARE interrupt is masked off then the timer must be rearmed in the callback, otherwise it will be rearmed next time the core goes to halt by the waiti instruction. Add test case into timer testsuite. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-10-01softmmu_header: pass CPUState to tlb_fillBlue Swirl
Pass CPUState pointer to tlb_fill() instead of architecture local cpu_single_env hacks. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10target-xtensa: add dc232b core and boardMax Filippov
This is Diamond 232L Standard Core Rev.B (LE). Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10target-xtensa: implement boolean optionMax Filippov
See ISA, 4.3.9 Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10target-xtensa: implement memory protection optionsMax Filippov
- TLB opcode group; - region protection option (ISA, 4.6.3); - region translation option (ISA, 4.6.4); - MMU option (ISA, 4.6.5). Cache control attribute bits are not used by this implementation. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10target-xtensa: add gdb supportMax Filippov
Specific xtensa processor overlay for GDB contains register map in the gdb/xtensa-config.c. This description is used by the GDB to e.g. parse 'g' response packets and it may be reused in the qemu's gdbstub (only XTREG definitions for non-pseudoregisters are needed). Currently mainline GDB does not support operations with privileged SRs (see http://sourceware.org/ml/gdb/2011-07/msg00075.html). This support may be enabled, see NUM_CORE_REGS comment in the gdbstub.c Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10target-xtensa: implement relocatable vectorsMax Filippov
See ISA, 4.4.3 for details. Vector addresses recorded in core configuration are absolute values that correspond to default VECBASE value. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10target-xtensa: implement CPENABLE and PRID SRsMax Filippov
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10target-xtensa: implement accurate window checkMax Filippov
See ISA, 4.7.1.3 for details. Window check is inserted before commands that push "used register watermark" beyond its current level. Used register watermark is reset on instructions that change WINDOW_BASE/WINDOW_START SRs. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10target-xtensa: implement interrupt optionMax Filippov
See ISA, 4.4.6 (interrupt option), 4.4.7 (high priority interrupt option) and 4.4.8 (timer interrupt option) for details. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10target-xtensa: implement SIMCALLMax Filippov
Tensilica iss provides support for applications running in freestanding environment through SIMCALL command. It is used by Tensilica libc to access argc/argv, for file I/O, etc. Note that simcalls that accept buffer addresses expect virtual addresses. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10target-xtensa: implement unaligned exception optionMax Filippov
See ISA, 4.4.4 for details. Correct (aligned as per ISA) address for unaligned access is generated in case this option is not enabled. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10target-xtensa: implement extended L32RMax Filippov
See ISA, 4.3.3 for details. TB flag XTENSA_TBFLAG_LITBASE is used to track enable bit of LITBASE SR. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10target-xtensa: implement loop optionMax Filippov
See ISA, 4.3.2 for details. Operations that change LEND SR value invalidate TBs at the old and at the new LEND. LEND value at TB compilation time is considered constant and loop instruction is generated based on this value. Invalidation may be avoided for the TB at the old LEND address, since looping code verifies actual LEND value. Invalidation may be avoided for the TB at the new LEND address if there's a way to associate LEND address with TB at compilation time and later verify that it doesn't change. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10target-xtensa: implement windowed registersMax Filippov
See ISA, 4.7.1 for details. Physical registers and currently visible window are separate fields in CPUEnv. Only current window is accessible to TCG. On operations that change window base helpers copy current window to and from physical registers. Window overflow check described in 4.7.1.3 is in separate patch. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10target-xtensa: implement RST2 group (32 bit mul/div/rem)Max Filippov
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10target-xtensa: implement exceptionsMax Filippov
- mark privileged opcodes with ring check; - make debug exception on exception handler entry. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10target-xtensa: add PS register and access controlMax Filippov
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10target-xtensa: implement CACHE groupMax Filippov
All operations in this group are no-ops, because cache ought to be transparent to applications. However cache may be abused, then we'll need to actually implement these opcodes. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10target-xtensa: implement SYNC groupMax Filippov
All operations in this group are no-ops, because there are no delayed side effects. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10target-xtensa: mark reserved and TBD opcodesMax Filippov
Reserved opcodes must generate illegal instruction exception. Usually they signal emulation quality problems. Not implemented opcodes are good to see. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10target-xtensa: implement LSAI groupMax Filippov
- base + offset load/store operations for 1/2/4 byte values; - cache operations (not implemented); - multiprocessor synchronization operations. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10target-xtensa: implement shifts (ST1 and RST1 groups)Max Filippov
- ST1: SAR (shift amount special register) manipulation, NSA(U); - RST1: shifts, 16-bit multiplication. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10target-xtensa: implement RST3 groupMax Filippov
- access to Special Registers (wsr, rsr); - access to User Registers (wur, rur); - misc. operations option (value clamp, sign extension, min, max); - conditional moves. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10target-xtensa: add special and user registersMax Filippov
Special Registers hold the majority of the state added to the processor by the options. See ISA, 5.3 for details. User Registers hold state added in support of designer's TIE and in some cases of options that Tensilica provides. See ISA, 5.4 for details. Only registers mapped in sregnames or uregnames are considered valid. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10target-xtensa: implement JX/RET0/CALLXMax Filippov
Group SNM0 (indirect jumps and calls). Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10target-xtensa: implement conditional jumpsMax Filippov
- BZ (comparison to zero); - BI0 (comparison to signed immediate); - BI1 (comparison to unsigned immediate); - B (two registers comparison, bit sets comparison); - BEQZ.N/BNEZ.N (narrow comparison to zero). Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10target-xtensa: implement RT0 groupMax Filippov
NEG and ABS are the only members of RT0 group. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10target-xtensa: implement narrow instructionsMax Filippov
Instructions with op0 >= 8 are 2 bytes long, others are 3 bytes long. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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