index
:
slackcoder/qemu
master
QEMU is a generic and open source machine & userspace emulator and virtualizer
Mirror
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
target-xtensa
/
translate.c
Age
Commit message (
Expand
)
Author
2012-11-10
target-xtensa: avoid using cpu_single_env
Blue Swirl
2012-10-06
target-xtensa: de-optimize EXTUI
Aurelien Jarno
2012-09-27
Emit debug_insn for CPU_LOG_TB_OP_OPT as well.
Richard Henderson
2012-09-22
target-xtensa: implement coprocessor context option
Max Filippov
2012-09-22
target-xtensa: implement FP1 group
Max Filippov
2012-09-22
target-xtensa: implement FP0 conversions
Max Filippov
2012-09-22
target-xtensa: implement FP0 arithmetic
Max Filippov
2012-09-22
target-xtensa: implement LSCX and LSCI groups
Max Filippov
2012-09-22
target-xtensa: add FP registers
Max Filippov
2012-09-21
target-xtensa: don't emit extra tcg_gen_goto_tb
Max Filippov
2012-09-21
target-xtensa: fix extui shift amount
Max Filippov
2012-07-28
target-xtensa: fix big-endian BBS/BBC implementation
Max Filippov
2012-06-10
target-xtensa: switch to AREG0-free mode
Max Filippov
2012-06-09
target-xtensa: fix CCOUNT for conditional branches
Max Filippov
2012-04-21
target-xtensa: fix LOOPNEZ/LOOPGTZ translation
Max Filippov
2012-04-14
target-xtensa: fix tb invalidation for IBREAK and LOOP
Max Filippov
2012-04-14
target-xtensa: Move helpers.h to helper.h
Lluís Vilanova
2012-03-14
target-xtensa: Don't overuse CPUState
Andreas Färber
2012-02-20
target-xtensa: add DBREAK data breakpoints
Max Filippov
2012-02-18
target-xtensa: add ICOUNT SR and debug exception
Max Filippov
2012-02-18
target-xtensa: implement instruction breakpoints
Max Filippov
2012-02-18
target-xtensa: add DEBUGCAUSE SR and configuration
Max Filippov
2012-02-18
target-xtensa: fetch 3rd opcode byte only when needed
Max Filippov
2011-11-02
target-xtensa: raise an exception for invalid and reserved opcodes
Max Filippov
2011-11-02
target-xtensa: mask out undefined bits of WINDOWSTART SR
Max Filippov
2011-10-16
target-xtensa: increase xtensa options accuracy
Max Filippov
2011-10-15
target-xtensa: implement MAC16 option
Max Filippov
2011-09-10
target-xtensa: implement boolean option
Max Filippov
2011-09-10
target-xtensa: implement memory protection options
Max Filippov
2011-09-10
target-xtensa: implement relocatable vectors
Max Filippov
2011-09-10
target-xtensa: implement CPENABLE and PRID SRs
Max Filippov
2011-09-10
target-xtensa: implement accurate window check
Max Filippov
2011-09-10
target-xtensa: implement interrupt option
Max Filippov
2011-09-10
target-xtensa: implement SIMCALL
Max Filippov
2011-09-10
target-xtensa: implement unaligned exception option
Max Filippov
2011-09-10
target-xtensa: implement extended L32R
Max Filippov
2011-09-10
target-xtensa: implement loop option
Max Filippov
2011-09-10
target-xtensa: implement windowed registers
Max Filippov
2011-09-10
target-xtensa: implement RST2 group (32 bit mul/div/rem)
Max Filippov
2011-09-10
target-xtensa: implement exceptions
Max Filippov
2011-09-10
target-xtensa: add PS register and access control
Max Filippov
2011-09-10
target-xtensa: implement CACHE group
Max Filippov
2011-09-10
target-xtensa: implement SYNC group
Max Filippov
2011-09-10
target-xtensa: mark reserved and TBD opcodes
Max Filippov
2011-09-10
target-xtensa: implement LSAI group
Max Filippov
2011-09-10
target-xtensa: implement shifts (ST1 and RST1 groups)
Max Filippov
2011-09-10
target-xtensa: implement RST3 group
Max Filippov
2011-09-10
target-xtensa: add special and user registers
Max Filippov
2011-09-10
target-xtensa: implement JX/RET0/CALLX
Max Filippov
2011-09-10
target-xtensa: implement conditional jumps
Max Filippov
[next]