Age | Commit message (Expand) | Author |
2014-02-24 | target-xtensa: provide HW confg ID registers | Max Filippov |
2014-02-24 | target-xtensa: add basic checks to icache opcodes | Max Filippov |
2014-02-24 | target-xtensa: add basic checks to dcache opcodes | Max Filippov |
2014-02-24 | target-xtensa: add RRRI4 opcode format fields | Max Filippov |
2013-10-15 | target-xtensa: add in_asm logging | Max Filippov |
2013-10-10 | tcg: Move helper registration into tcg_context_init | Richard Henderson |
2013-09-02 | tcg: Change tcg_gen_exit_tb argument to uintptr_t | Richard Henderson |
2013-07-29 | target-xtensa: check register window inline | Max Filippov |
2013-07-29 | target-xtensa: don't generate dead code to access invalid SRs | Max Filippov |
2013-07-29 | target-xtensa: avoid double-stopping at breakpoints | Max Filippov |
2013-07-23 | cpu: Move singlestep_enabled field from CPU_COMMON to CPUState | Andreas Färber |
2013-07-09 | target-xtensa: Change gen_intermediate_code_internal() arg to XtensaCPU | Andreas Färber |
2013-07-09 | target-xtensa: gen_intermediate_code_internal() should be inlined | Andreas Färber |
2013-06-28 | cpu: Turn cpu_dump_{state,statistics}() into CPUState hooks | Andreas Färber |
2013-03-03 | gen-icount.h: Rename gen_icount_start/end to gen_tb_start/end | Peter Maydell |
2013-02-23 | target-xtensa: Use add2/sub2 for mac | Richard Henderson |
2013-02-23 | target-xtensa: Use mul*2 for mul*hi | Richard Henderson |
2012-12-22 | target-xtensa: fix search_pc for the last TB opcode | Max Filippov |
2012-12-19 | softmmu: move include files to include/sysemu/ | Paolo Bonzini |
2012-12-19 | misc: move include files to include/qemu/ | Paolo Bonzini |
2012-12-19 | exec: move include files to include/exec/ | Paolo Bonzini |
2012-12-19 | build: kill libdis, move disassemblers to disas/ | Paolo Bonzini |
2012-12-08 | target-xtensa: use movcond where possible | Max Filippov |
2012-12-08 | target-xtensa: implement MISC SR | Max Filippov |
2012-12-08 | target-xtensa: better control rsr/wsr/xsr access to SRs | Max Filippov |
2012-12-08 | target-xtensa: restrict available SRs by enabled options | Max Filippov |
2012-12-08 | target-xtensa: implement CACHEATTR SR | Max Filippov |
2012-12-08 | target-xtensa: implement ATOMCTL SR | Max Filippov |
2012-12-08 | TCG: Use gen_opc_instr_start from context instead of global variable. | Evgeny Voevodin |
2012-12-08 | TCG: Use gen_opc_icount from context instead of global variable. | Evgeny Voevodin |
2012-12-08 | TCG: Use gen_opc_pc from context instead of global variable. | Evgeny Voevodin |
2012-11-17 | TCG: Use gen_opc_buf from context instead of global variable. | Evgeny Voevodin |
2012-11-17 | TCG: Use gen_opc_ptr from context instead of global variable. | Evgeny Voevodin |
2012-11-10 | target-xtensa: avoid using cpu_single_env | Blue Swirl |
2012-10-06 | target-xtensa: de-optimize EXTUI | Aurelien Jarno |
2012-09-27 | Emit debug_insn for CPU_LOG_TB_OP_OPT as well. | Richard Henderson |
2012-09-22 | target-xtensa: implement coprocessor context option | Max Filippov |
2012-09-22 | target-xtensa: implement FP1 group | Max Filippov |
2012-09-22 | target-xtensa: implement FP0 conversions | Max Filippov |
2012-09-22 | target-xtensa: implement FP0 arithmetic | Max Filippov |
2012-09-22 | target-xtensa: implement LSCX and LSCI groups | Max Filippov |
2012-09-22 | target-xtensa: add FP registers | Max Filippov |
2012-09-21 | target-xtensa: don't emit extra tcg_gen_goto_tb | Max Filippov |
2012-09-21 | target-xtensa: fix extui shift amount | Max Filippov |
2012-07-28 | target-xtensa: fix big-endian BBS/BBC implementation | Max Filippov |
2012-06-10 | target-xtensa: switch to AREG0-free mode | Max Filippov |
2012-06-09 | target-xtensa: fix CCOUNT for conditional branches | Max Filippov |
2012-04-21 | target-xtensa: fix LOOPNEZ/LOOPGTZ translation | Max Filippov |
2012-04-14 | target-xtensa: fix tb invalidation for IBREAK and LOOP | Max Filippov |
2012-04-14 | target-xtensa: Move helpers.h to helper.h | Lluís Vilanova |