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QEMU is a generic and open source machine & userspace emulator and virtualizer
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target-xtensa
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translate.c
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Author
2015-10-21
target-xtensa: implement S32NB
Max Filippov
2015-10-21
target-xtensa: implement depbits instruction
Max Filippov
2015-10-21
target-xtensa: add window overflow check to L32E/S32E
Max Filippov
2015-10-07
tcg: Remove gen_intermediate_code_pc
Richard Henderson
2015-10-07
tcg: Pass data argument to restore_state_to_opc
Richard Henderson
2015-10-07
tcg: Add TCG_MAX_INSNS
Richard Henderson
2015-10-07
target-*: Introduce and use cpu_breakpoint_test
Richard Henderson
2015-10-07
target-*: Increment num_insns immediately after tcg_gen_insn_start
Richard Henderson
2015-10-07
target-*: Unconditionally emit tcg_gen_insn_start
Richard Henderson
2015-10-07
tcg: Rename debug_insn_start to insn_start
Richard Henderson
2015-08-24
tcg: Remove tcg_gen_trunc_i64_i32
Richard Henderson
2015-07-06
target-xtensa: add 64-bit floating point registers
Max Filippov
2015-06-22
disas: Remove uses of CPU env
Peter Crosthwaite
2015-06-19
semihosting: create SemihostingConfig structure and semihost.h
Leon Alrae
2015-03-13
tcg: Change translator-side labels to a pointer
Richard Henderson
2015-02-12
tcg: Introduce tcg_op_buf_count and tcg_op_buf_full
Richard Henderson
2015-02-12
tcg: Move emit of INDEX_op_end into gen_tb_end
Richard Henderson
2015-01-03
gen-icount: check cflags instead of use_icount global
Paolo Bonzini
2014-12-17
target-xtensa: don't generate dead code
Max Filippov
2014-12-17
target-xtensa: record available window in TB flags
Max Filippov
2014-12-17
target-xtensa: fix translation for opcodes crossing page boundary
Max Filippov
2014-08-12
trace: [tcg] Include TCG-tracing header on all targets
Lluís Vilanova
2014-06-05
softmmu: introduce cpu_ldst.h
Paolo Bonzini
2014-05-28
tcg: Invert the inclusion of helper.h
Richard Henderson
2014-05-26
target-xtensa: fix cross-page jumps/calls at the end of TB
Max Filippov
2014-03-13
cpu: Move breakpoints field from CPU_COMMON to CPUState
Andreas Färber
2014-02-24
target-xtensa: provide HW confg ID registers
Max Filippov
2014-02-24
target-xtensa: add basic checks to icache opcodes
Max Filippov
2014-02-24
target-xtensa: add basic checks to dcache opcodes
Max Filippov
2014-02-24
target-xtensa: add RRRI4 opcode format fields
Max Filippov
2013-10-15
target-xtensa: add in_asm logging
Max Filippov
2013-10-10
tcg: Move helper registration into tcg_context_init
Richard Henderson
2013-09-02
tcg: Change tcg_gen_exit_tb argument to uintptr_t
Richard Henderson
2013-07-29
target-xtensa: check register window inline
Max Filippov
2013-07-29
target-xtensa: don't generate dead code to access invalid SRs
Max Filippov
2013-07-29
target-xtensa: avoid double-stopping at breakpoints
Max Filippov
2013-07-23
cpu: Move singlestep_enabled field from CPU_COMMON to CPUState
Andreas Färber
2013-07-09
target-xtensa: Change gen_intermediate_code_internal() arg to XtensaCPU
Andreas Färber
2013-07-09
target-xtensa: gen_intermediate_code_internal() should be inlined
Andreas Färber
2013-06-28
cpu: Turn cpu_dump_{state,statistics}() into CPUState hooks
Andreas Färber
2013-03-03
gen-icount.h: Rename gen_icount_start/end to gen_tb_start/end
Peter Maydell
2013-02-23
target-xtensa: Use add2/sub2 for mac
Richard Henderson
2013-02-23
target-xtensa: Use mul*2 for mul*hi
Richard Henderson
2012-12-22
target-xtensa: fix search_pc for the last TB opcode
Max Filippov
2012-12-19
softmmu: move include files to include/sysemu/
Paolo Bonzini
2012-12-19
misc: move include files to include/qemu/
Paolo Bonzini
2012-12-19
exec: move include files to include/exec/
Paolo Bonzini
2012-12-19
build: kill libdis, move disassemblers to disas/
Paolo Bonzini
2012-12-08
target-xtensa: use movcond where possible
Max Filippov
2012-12-08
target-xtensa: implement MISC SR
Max Filippov
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