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path: root/target-xtensa/translate.c
AgeCommit message (Expand)Author
2015-10-07tcg: Remove gen_intermediate_code_pcRichard Henderson
2015-10-07tcg: Pass data argument to restore_state_to_opcRichard Henderson
2015-10-07tcg: Add TCG_MAX_INSNSRichard Henderson
2015-10-07target-*: Introduce and use cpu_breakpoint_testRichard Henderson
2015-10-07target-*: Increment num_insns immediately after tcg_gen_insn_startRichard Henderson
2015-10-07target-*: Unconditionally emit tcg_gen_insn_startRichard Henderson
2015-10-07tcg: Rename debug_insn_start to insn_startRichard Henderson
2015-08-24tcg: Remove tcg_gen_trunc_i64_i32Richard Henderson
2015-07-06target-xtensa: add 64-bit floating point registersMax Filippov
2015-06-22disas: Remove uses of CPU envPeter Crosthwaite
2015-06-19semihosting: create SemihostingConfig structure and semihost.hLeon Alrae
2015-03-13tcg: Change translator-side labels to a pointerRichard Henderson
2015-02-12tcg: Introduce tcg_op_buf_count and tcg_op_buf_fullRichard Henderson
2015-02-12tcg: Move emit of INDEX_op_end into gen_tb_endRichard Henderson
2015-01-03gen-icount: check cflags instead of use_icount globalPaolo Bonzini
2014-12-17target-xtensa: don't generate dead codeMax Filippov
2014-12-17target-xtensa: record available window in TB flagsMax Filippov
2014-12-17target-xtensa: fix translation for opcodes crossing page boundaryMax Filippov
2014-08-12trace: [tcg] Include TCG-tracing header on all targetsLluís Vilanova
2014-06-05softmmu: introduce cpu_ldst.hPaolo Bonzini
2014-05-28tcg: Invert the inclusion of helper.hRichard Henderson
2014-05-26target-xtensa: fix cross-page jumps/calls at the end of TBMax Filippov
2014-03-13cpu: Move breakpoints field from CPU_COMMON to CPUStateAndreas Färber
2014-02-24target-xtensa: provide HW confg ID registersMax Filippov
2014-02-24target-xtensa: add basic checks to icache opcodesMax Filippov
2014-02-24target-xtensa: add basic checks to dcache opcodesMax Filippov
2014-02-24target-xtensa: add RRRI4 opcode format fieldsMax Filippov
2013-10-15target-xtensa: add in_asm loggingMax Filippov
2013-10-10tcg: Move helper registration into tcg_context_initRichard Henderson
2013-09-02tcg: Change tcg_gen_exit_tb argument to uintptr_tRichard Henderson
2013-07-29target-xtensa: check register window inlineMax Filippov
2013-07-29target-xtensa: don't generate dead code to access invalid SRsMax Filippov
2013-07-29target-xtensa: avoid double-stopping at breakpointsMax Filippov
2013-07-23cpu: Move singlestep_enabled field from CPU_COMMON to CPUStateAndreas Färber
2013-07-09target-xtensa: Change gen_intermediate_code_internal() arg to XtensaCPUAndreas Färber
2013-07-09target-xtensa: gen_intermediate_code_internal() should be inlinedAndreas Färber
2013-06-28cpu: Turn cpu_dump_{state,statistics}() into CPUState hooksAndreas Färber
2013-03-03gen-icount.h: Rename gen_icount_start/end to gen_tb_start/endPeter Maydell
2013-02-23target-xtensa: Use add2/sub2 for macRichard Henderson
2013-02-23target-xtensa: Use mul*2 for mul*hiRichard Henderson
2012-12-22target-xtensa: fix search_pc for the last TB opcodeMax Filippov
2012-12-19softmmu: move include files to include/sysemu/Paolo Bonzini
2012-12-19misc: move include files to include/qemu/Paolo Bonzini
2012-12-19exec: move include files to include/exec/Paolo Bonzini
2012-12-19build: kill libdis, move disassemblers to disas/Paolo Bonzini
2012-12-08target-xtensa: use movcond where possibleMax Filippov
2012-12-08target-xtensa: implement MISC SRMax Filippov
2012-12-08target-xtensa: better control rsr/wsr/xsr access to SRsMax Filippov
2012-12-08target-xtensa: restrict available SRs by enabled optionsMax Filippov
2012-12-08target-xtensa: implement CACHEATTR SRMax Filippov
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