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path: root/target-xtensa/cpu.h
AgeCommit message (Expand)Author
2014-11-03target-xtensa: add definition for XTHAL_INTTYPE_PROFILINGMax Filippov
2014-09-12cpu-exec: Make debug_excp_handler a QOM CPU methodPeter Maydell
2014-06-05softmmu: move ALIGNED_ONLY to cpu.hPaolo Bonzini
2014-03-13cpu: Move watchpoint fields from CPU_COMMON to CPUStateAndreas Färber
2014-03-13cpu: Turn cpu_has_work() into a CPUClass hookAndreas Färber
2014-03-13target-xtensa: Clean up ENV_GET_CPU() usageAndreas Färber
2014-02-24target-xtensa: provide HW confg ID registersMax Filippov
2013-07-29target-xtensa: avoid double-stopping at breakpointsMax Filippov
2013-07-23cpu: Introduce CPUClass::synchronize_from_tb() for cpu_pc_from_tb()Andreas Färber
2013-03-12cpu: Replace do_interrupt() by CPUClass::do_interrupt methodAndreas Färber
2013-02-16target-xtensa: Move TCG initialization to XtensaCPU initfnAndreas Färber
2012-12-19exec: move include files to include/exec/Paolo Bonzini
2012-12-08target-xtensa: implement MISC SRMax Filippov
2012-12-08target-xtensa: restrict available SRs by enabled optionsMax Filippov
2012-12-08target-xtensa: implement CACHEATTR SRMax Filippov
2012-12-08target-xtensa: implement ATOMCTL SRMax Filippov
2012-10-31cpus: Pass CPUState to [qemu_]cpu_has_work()Andreas Färber
2012-09-22target-xtensa: implement coprocessor context optionMax Filippov
2012-09-22target-xtensa: add FP registersMax Filippov
2012-08-09target-xtensa: make default CPU depend on target endiannessMax Filippov
2012-06-09target-xtensa: update autorefill TLB entries conditionallyMax Filippov
2012-06-09target-xtensa: extract TLB entry setting methodMax Filippov
2012-06-04target-xtensa: Let cpu_xtensa_init() return XtensaCPUAndreas Färber
2012-04-14target-xtensa: QOM'ify CPU resetAndreas Färber
2012-04-14target-xtensa: QOM'ify CPUAndreas Färber
2012-03-14Rename CPUState -> CPUArchStateAndreas Färber
2012-03-14target-xtensa: Don't overuse CPUStateAndreas Färber
2012-02-20target-xtensa: add DBREAK data breakpointsMax Filippov
2012-02-18target-xtensa: add ICOUNT SR and debug exceptionMax Filippov
2012-02-18target-xtensa: implement instruction breakpointsMax Filippov
2012-02-18target-xtensa: add DEBUGCAUSE SR and configurationMax Filippov
2012-02-18target-xtensa: implement info tlb monitor commandMax Filippov
2011-10-16target-xtensa: extract core configuration from overlayMax Filippov
2011-10-16target-xtensa: implement external interrupt mappingMax Filippov
2011-10-16target-xtensa: increase xtensa options accuracyMax Filippov
2011-10-15target-xtensa: implement MAC16 optionMax Filippov
2011-10-15target-xtensa: fix guest hang on masked CCOMPARE interruptMax Filippov
2011-09-10target-xtensa: implement boolean optionMax Filippov
2011-09-10target-xtensa: implement memory protection optionsMax Filippov
2011-09-10target-xtensa: add gdb supportMax Filippov
2011-09-10target-xtensa: implement relocatable vectorsMax Filippov
2011-09-10target-xtensa: implement CPENABLE and PRID SRsMax Filippov
2011-09-10target-xtensa: implement interrupt optionMax Filippov
2011-09-10target-xtensa: implement extended L32RMax Filippov
2011-09-10target-xtensa: implement loop optionMax Filippov
2011-09-10target-xtensa: implement windowed registersMax Filippov
2011-09-10target-xtensa: implement exceptionsMax Filippov
2011-09-10target-xtensa: add PS register and access controlMax Filippov
2011-09-10target-xtensa: implement LSAI groupMax Filippov
2011-09-10target-xtensa: implement shifts (ST1 and RST1 groups)Max Filippov
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