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AgeCommit message (Expand)Author
2015-01-26target-tricore: Several translator and cpu model fixesBastian Koppelmann
2015-01-26target-tricore: Add missing ULL suffix on 64 bit constantPeter Maydell
2015-01-15target-tricore: Fix new typosStefan Weil
2015-01-09Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell
2015-01-03gen-icount: check cflags instead of use_icount globalPaolo Bonzini
2014-12-21target-tricore: Add instructions of RR1 opcode format, that have 0xb3 as firs...Bastian Koppelmann
2014-12-21target-tricore: Fix MFCR/MTCR insn and B format offset.Bastian Koppelmann
2014-12-21target-tricore: Add missing 1.6 insn of BOL opcode formatBastian Koppelmann
2014-12-21target-tricore: Add instructions of RR opcode format, that have 0x4b as the f...Bastian Koppelmann
2014-12-21target-tricore: Add instructions of RR opcode format, that have 0x1 as the fi...Bastian Koppelmann
2014-12-21target-tricore: Add instructions of RR opcode format, that have 0xf as the fi...Bastian Koppelmann
2014-12-21target-tricore: Add instructions of RR opcode format, that have 0xb as the fi...Bastian Koppelmann
2014-12-21target-tricore: Change SSOV/SUOV makro name to SSOV32/SUOV32Bastian Koppelmann
2014-12-21target-tricore: Fix mask handling JNZ.T being 7 bit longBastian Koppelmann
2014-12-21target-tricore: pretty-print register dump and show more status registersAlex Zuepke
2014-12-21target-tricore: add missing 64-bit MOV in RLC formatAlex Zuepke
2014-12-21target-tricore: typo in BOL formatAlex Zuepke
2014-12-21target-tricore: fix offset masking in BOL formatAlex Zuepke
2014-12-10target-tricore: Add instructions of RCR opcode formatBastian Koppelmann
2014-12-10target-tricore: Add instructions of RLC opcode formatBastian Koppelmann
2014-12-10target-tricore: Add instructions of RCPW, RCRR and RCRW opcode formatBastian Koppelmann
2014-12-10target-tricore: Make TRICORE_FEATURES implying others.Bastian Koppelmann
2014-12-10target-tricore: Add instructions of RC opcode formatBastian Koppelmann
2014-12-10target-tricore: Add instructions of BRR opcode formatBastian Koppelmann
2014-12-10target-tricore: Add instructions of BRN opcode formatBastian Koppelmann
2014-12-10target-tricore: Add instructions of BRC opcode formatBastian Koppelmann
2014-12-10target-tricore: Add instructions of BOL opcode formatBastian Koppelmann
2014-10-20target-tricore: Add instructions of BO opcode formatBastian Koppelmann
2014-10-20target-tricore: Add instructions of BIT opcode formatBastian Koppelmann
2014-10-20target-tricore: Add instructions of B opcode formatBastian Koppelmann
2014-10-20target-tricore: Add instructions of ABS, ABSB opcode formatBastian Koppelmann
2014-10-20target-tricore: Cleanup and BugfixesBastian Koppelmann
2014-09-25target-tricore: Remove the dummy interrupt boilerplateRichard Henderson
2014-09-01target-tricore: Add instructions of SR opcode formatBastian Koppelmann
2014-09-01target-tricore: Add instructions of SLR, SSRO and SRO opcode formatBastian Koppelmann
2014-09-01target-tricore: Add instructions of SC opcode formatBastian Koppelmann
2014-09-01target-tricore: Add instructions of SBR opcode formatBastian Koppelmann
2014-09-01target-tricore: Add instructions of SBC and SBRN opcode formatBastian Koppelmann
2014-09-01target-tricore: Add instructions of SB opcode formatBastian Koppelmann
2014-09-01target-tricore: Add instructions of SRRS and SLRO opcode formatBastian Koppelmann
2014-09-01target-tricore: Add instructions of SSR opcode formatBastian Koppelmann
2014-09-01target-tricore: Add instructions of SRR opcode formatBastian Koppelmann
2014-09-01target-tricore: Add instructions of SRC opcode formatBastian Koppelmann
2014-09-01target-tricore: Add masks and opcodes for decodingBastian Koppelmann
2014-09-01target-tricore: Add initialization for translation and activate targetBastian Koppelmann
2014-09-01target-tricore: Add softmmu supportBastian Koppelmann
2014-09-01target-tricore: Add target stubs and qom-cpuBastian Koppelmann
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