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AgeCommit message (Expand)Author
2015-10-09qdev: Protect device-list-properties against broken devicesMarkus Armbruster
2015-10-07tcg: Remove gen_intermediate_code_pcRichard Henderson
2015-10-07tcg: Pass data argument to restore_state_to_opcRichard Henderson
2015-10-07tcg: Add TCG_MAX_INSNSRichard Henderson
2015-10-07target-*: Increment num_insns immediately after tcg_gen_insn_startRichard Henderson
2015-10-07target-*: Unconditionally emit tcg_gen_insn_startRichard Henderson
2015-09-25tricore: Remove ELF_MACHINE from cpu.hPeter Crosthwaite
2015-09-11tlb: Add "ifetch" argument to cpu_mmu_index()Benjamin Herrenschmidt
2015-09-11maint: remove unused include for signal.hDaniel P. Berrange
2015-08-24tcg: Remove tcg_gen_trunc_i64_i32Richard Henderson
2015-08-24tcg: Split trunc_shr_i32 opcode into extr[lh]_i64_i32Richard Henderson
2015-07-09cpu-exec: Purge all uses of ENV_GET_CPU()Peter Crosthwaite
2015-07-09cpu: Change cpu_exec_init() arg to cpu, not envPeter Crosthwaite
2015-07-09cpu: Add Error argument to cpu_exec_init()Bharata B Rao
2015-06-29target-tricore: fix depositing bits from PCXI into ICRPaolo Bonzini
2015-06-22disas: Remove uses of CPU envPeter Crosthwaite
2015-05-30target-tricore: fix BOL_ST_H_LONGOFF using ldBastian Koppelmann
2015-05-30target-tricore: fix msub32_q producing the wrong overflow bitBastian Koppelmann
2015-05-30target-tricore: fix OPC2_32_RR_DVINIT_HU having write before use on the resultBastian Koppelmann
2015-05-22target-tricore: add RR_DIV and RR_DIV_U instructions of the v1.6 ISABastian Koppelmann
2015-05-22target-tricore: add FRET instructions of the v1.6 ISABastian Koppelmann
2015-05-22target-tricore: add FCALL instructions of the v1.6 ISABastian Koppelmann
2015-05-22target-tricore: add SYS_RESTORE instruction of the v1.6 ISABastian Koppelmann
2015-05-22target-tricore: add RR_CRC32 instruction of the v1.6.1 ISABastian Koppelmann
2015-05-22target-tricore: add SWAPMSK instructions of the v1.6.1 ISABastian Koppelmann
2015-05-22target-tricore: add CMPSWP instructions of the v1.6.1 ISABastian Koppelmann
2015-05-22target-tricore: Add SRC_MOV_E instruction of the v1.6 ISABastian Koppelmann
2015-05-22target-tricore: introduce ISA v1.6.1 featureBastian Koppelmann
2015-05-22target-tricore: Add ISA v1.3.1 cpu and fix tc1796 to using v1.3Bastian Koppelmann
2015-05-11target-tricore: fix rfe not restoring the PCBastian Koppelmann
2015-05-11target-tricore: fix rslcx restoring the upper context instead of the lowerBastian Koppelmann
2015-05-11target-tricore: fix BO_OFF10_SEXT calculating the wrong offsetBastian Koppelmann
2015-05-11target-tricore: fix SLR_LD_W and SLR_LD_W_POSTINC insn being a 2 byte memory ...Bastian Koppelmann
2015-05-11target-tricore: Fix LOOP using wrong register for compareBastian Koppelmann
2015-04-30tcg: Delete unused cpu_pc_from_tb()Peter Crosthwaite
2015-04-04target-tricore: Fix check which was always falseStefan Weil
2015-03-30target-tricore: fix CACHEA/I_POSTINC/PREINC using data register..Bastian Koppelmann
2015-03-24target-tricore: properly fix dvinit_b/h_13Bastian Koppelmann
2015-03-24target-tricore: fix RRPW_DEXTR using wrong regBastian Koppelmann
2015-03-24target-tricore: fix DVINIT_HU/BU calculating overflow before resultBastian Koppelmann
2015-03-24target-tricore: Fix two helper functions (clang warnings)Stefan Weil
2015-03-19Fix typos in commentsViswesh
2015-03-16target-tricore: Add instructions of SYS opcode formatBastian Koppelmann
2015-03-16target-tricore: Add instructions of RRRW opcode formatBastian Koppelmann
2015-03-16target-tricore: Add instructions of RRRR opcode formatBastian Koppelmann
2015-03-16target-tricore: Add instructions of RRR1 opcode format, which have 0xe3 as fi...Bastian Koppelmann
2015-03-16target-tricore: Add instructions of RRR1 opcode format, which have 0x63 as fi...Bastian Koppelmann
2015-03-16target-tricore: Add instructions of RRR1 opcode format, which have 0xa3 as fi...Bastian Koppelmann
2015-03-13tcg: Change translator-side labels to a pointerRichard Henderson
2015-03-10cpu: Make cpu_init() return QOM CPUState objectEduardo Habkost
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