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AgeCommit message (Expand)Author
2015-07-09cpu: Add Error argument to cpu_exec_init()Bharata B Rao
2015-06-29target-tricore: fix depositing bits from PCXI into ICRPaolo Bonzini
2015-06-22disas: Remove uses of CPU envPeter Crosthwaite
2015-05-30target-tricore: fix BOL_ST_H_LONGOFF using ldBastian Koppelmann
2015-05-30target-tricore: fix msub32_q producing the wrong overflow bitBastian Koppelmann
2015-05-30target-tricore: fix OPC2_32_RR_DVINIT_HU having write before use on the resultBastian Koppelmann
2015-05-22target-tricore: add RR_DIV and RR_DIV_U instructions of the v1.6 ISABastian Koppelmann
2015-05-22target-tricore: add FRET instructions of the v1.6 ISABastian Koppelmann
2015-05-22target-tricore: add FCALL instructions of the v1.6 ISABastian Koppelmann
2015-05-22target-tricore: add SYS_RESTORE instruction of the v1.6 ISABastian Koppelmann
2015-05-22target-tricore: add RR_CRC32 instruction of the v1.6.1 ISABastian Koppelmann
2015-05-22target-tricore: add SWAPMSK instructions of the v1.6.1 ISABastian Koppelmann
2015-05-22target-tricore: add CMPSWP instructions of the v1.6.1 ISABastian Koppelmann
2015-05-22target-tricore: Add SRC_MOV_E instruction of the v1.6 ISABastian Koppelmann
2015-05-22target-tricore: introduce ISA v1.6.1 featureBastian Koppelmann
2015-05-22target-tricore: Add ISA v1.3.1 cpu and fix tc1796 to using v1.3Bastian Koppelmann
2015-05-11target-tricore: fix rfe not restoring the PCBastian Koppelmann
2015-05-11target-tricore: fix rslcx restoring the upper context instead of the lowerBastian Koppelmann
2015-05-11target-tricore: fix BO_OFF10_SEXT calculating the wrong offsetBastian Koppelmann
2015-05-11target-tricore: fix SLR_LD_W and SLR_LD_W_POSTINC insn being a 2 byte memory ...Bastian Koppelmann
2015-05-11target-tricore: Fix LOOP using wrong register for compareBastian Koppelmann
2015-04-30tcg: Delete unused cpu_pc_from_tb()Peter Crosthwaite
2015-04-04target-tricore: Fix check which was always falseStefan Weil
2015-03-30target-tricore: fix CACHEA/I_POSTINC/PREINC using data register..Bastian Koppelmann
2015-03-24target-tricore: properly fix dvinit_b/h_13Bastian Koppelmann
2015-03-24target-tricore: fix RRPW_DEXTR using wrong regBastian Koppelmann
2015-03-24target-tricore: fix DVINIT_HU/BU calculating overflow before resultBastian Koppelmann
2015-03-24target-tricore: Fix two helper functions (clang warnings)Stefan Weil
2015-03-19Fix typos in commentsViswesh
2015-03-16target-tricore: Add instructions of SYS opcode formatBastian Koppelmann
2015-03-16target-tricore: Add instructions of RRRW opcode formatBastian Koppelmann
2015-03-16target-tricore: Add instructions of RRRR opcode formatBastian Koppelmann
2015-03-16target-tricore: Add instructions of RRR1 opcode format, which have 0xe3 as fi...Bastian Koppelmann
2015-03-16target-tricore: Add instructions of RRR1 opcode format, which have 0x63 as fi...Bastian Koppelmann
2015-03-16target-tricore: Add instructions of RRR1 opcode format, which have 0xa3 as fi...Bastian Koppelmann
2015-03-13tcg: Change translator-side labels to a pointerRichard Henderson
2015-03-10cpu: Make cpu_init() return QOM CPUState objectEduardo Habkost
2015-03-03target-tricore: Add instructions of RRR1 opcode format, which have 0xc3 as fi...Bastian Koppelmann
2015-03-03target-tricore: Add instructions of RRR1 opcode format, which have 0x43 as fi...Bastian Koppelmann
2015-03-03target-tricore: Add instructions of RRR1 opcode format, which have 0x83 as fi...Bastian Koppelmann
2015-03-03target-tricore: Add instructions of RRR2 opcode formatBastian Koppelmann
2015-03-03target-tricore: fix msub32_suov return wrong resultsBastian Koppelmann
2015-03-03target-tricore: Fix RLC_ADDI, RLC_ADDIH using wrong microcode helperBastian Koppelmann
2015-02-12tcg: Introduce tcg_op_buf_count and tcg_op_buf_fullRichard Henderson
2015-02-12tcg: Move emit of INDEX_op_end into gen_tb_endRichard Henderson
2015-01-27target-tricore: Add instructions of RRR opcode formatBastian Koppelmann
2015-01-27target-tricore: Add instructions of RRPW opcode formatBastian Koppelmann
2015-01-27target-tricore: Add instructions of RR2 opcode formatBastian Koppelmann
2015-01-27target-tricore: Add instructions of RR1 opcode format, that have 0x93 as firs...Bastian Koppelmann
2015-01-26target-tricore: split up suov32 into suov32_pos and suov32_negBastian Koppelmann
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