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2016-05-19cpu: move exec-all.h inclusion out of cpu.hPaolo Bonzini
exec-all.h contains TCG-specific definitions. It is not needed outside TCG-specific files such as translate.c, exec.c or *helper.c. One generic function had snuck into include/exec/exec-all.h; move it to include/qom/cpu.h. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-05-18Fix some typos found by codespellStefan Weil
Signed-off-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2016-05-12tcg: Allow goto_tb to any target PC in user modeSergey Fedorov
In user mode, there's only a static address translation, TBs are always invalidated properly and direct jumps are reset when mapping change. Thus the destination address is always valid for direct jumps and there's no need to restrict it to the pages the TB resides in. Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com> Signed-off-by: Sergey Fedorov <sergey.fedorov@linaro.org> Cc: Riku Voipio <riku.voipio@iki.fi> Cc: Blue Swirl <blauwirbel@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-03-23target-tricore: Add ftoi and itof instructionsBastian Koppelmann
Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <1457708597-3025-8-git-send-email-kbastian@mail.uni-paderborn.de>
2016-03-23target-tricore: Add cmp.f instructionBastian Koppelmann
Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <1457708597-3025-7-git-send-email-kbastian@mail.uni-paderborn.de>
2016-03-23target-tricore: Add div.f instructionBastian Koppelmann
Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <1457708597-3025-6-git-send-email-kbastian@mail.uni-paderborn.de>
2016-03-23target-tricore: Add mul.f instructionBastian Koppelmann
Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <1457708597-3025-5-git-send-email-kbastian@mail.uni-paderborn.de>
2016-03-23target-tricore: add add.f/sub.f instructionsBastian Koppelmann
Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <1457708597-3025-4-git-send-email-kbastian@mail.uni-paderborn.de>
2016-03-23target-tricore: Move general CHECK_REG_PAIR of decode_rrr_divideBastian Koppelmann
The add.f and sub.f to be implemented don't use 64 bit registers and a general usage of CHECK_REG_PAIR would always generate an exception for them. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <1457708597-3025-3-git-send-email-kbastian@mail.uni-paderborn.de>
2016-03-23target-tricore: Add FPU infrastructureBastian Koppelmann
This patch adds a file for all the FPU related helpers with all the includes, useful defines, and a function to update the status bits. Additionally it adds a mask for the rounding mode bits of PSW as well as all the opcodes for the FPU instructions. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <1457708597-3025-2-git-send-email-kbastian@mail.uni-paderborn.de>
2016-03-23target-tricore: add missing break in insn decode switch stmtBastian Koppelmann
After decoding/translating a RRR_DIVIDE/RRRR_EXTRACT_INSERT type instruction we would simply fall through and would decode/translate another unintended RRR2_MADD/RRRW_EXTRACT_INSERT instruction. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <1458547383-23102-2-git-send-email-kbastian@mail.uni-paderborn.de>
2016-03-01tcg: Add type for vCPU pointersLluís Vilanova
Adds the 'TCGv_env' type for pointers to 'CPUArchState' objects. The tracing infrastructure later needs to differentiate between regular pointers and pointers to vCPUs. Also changes all targets to use the new 'TCGv_env' type instead of the generic 'TCGv_ptr'. As of now, the change is merely cosmetic ('TCGv_env' translates into 'TCGv_ptr'), but that could change in the future to enforce the difference. Note that a 'TCGv_env' type (for 'CPUState') is not added, since all helpers currently receive the architecture-specific pointer ('CPUArchState'). Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Acked-by: Richard Henderson <rth@twiddle.net> Message-id: 145641859552.30295.7821536833590725201.stgit@localhost Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2016-02-25target-tricore: add opd trap generationBastian Koppelmann
If an instruction uses a 64 bit register which consists of an even-odd pair of 32 bit registers and if the register specifier in the instruction is odd an opd trap is raised. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <1455889426-1923-5-git-send-email-kbastian@mail.uni-paderborn.de>
2016-02-25target-tricore: add illegal opcode trap generationBastian Koppelmann
Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <1455889426-1923-4-git-send-email-kbastian@mail.uni-paderborn.de>
2016-02-25target-tricore: Add trap handling & SOVF/OVF trapsBastian Koppelmann
Add the infrastructure needed to generate and handle traps and implement the generation of SOVF and OVF traps. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <1455889426-1923-2-git-send-email-kbastian@mail.uni-paderborn.de>
2016-02-09tcg: Change tcg_global_mem_new_* to take a TCGv_ptrRichard Henderson
Thus, use cpu_env as the parameter, not TCG_AREG0 directly. Update all uses in the translators. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-02-03log: do not unnecessarily include qom/cpu.hPaolo Bonzini
Split the bits that require it to exec/log.h. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Denis V. Lunev <den@openvz.org> Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> Message-id: 1452174932-28657-8-git-send-email-den@openvz.org Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2016-01-29tricore: Clean up includesPeter Maydell
Clean up includes so that osdep.h is included first and headers which it implies are not included manually. This commit was created with scripts/clean-includes. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1453832250-766-34-git-send-email-peter.maydell@linaro.org
2015-10-07tcg: Remove gen_intermediate_code_pcRichard Henderson
It is no longer used, so tidy up everything reached by it. This includes the gen_opc_* arrays, the search_pc parameter and the inline gen_intermediate_code_internal functions. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07tcg: Pass data argument to restore_state_to_opcRichard Henderson
The gen_opc_* arrays are already redundant with the data stored in the insn_start arguments. Transition restore_state_to_opc to use data from the latter. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07tcg: Add TCG_MAX_INSNSRichard Henderson
Adjust all translators to respect it. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07target-*: Increment num_insns immediately after tcg_gen_insn_startRichard Henderson
This does tidy the icount test common to all targets. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07target-*: Unconditionally emit tcg_gen_insn_startRichard Henderson
While we're at it, emit the opcode adjacent to where we currently record data for search_pc. This puts gen_io_start et al on the "correct" side of the marker. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-11tlb: Add "ifetch" argument to cpu_mmu_index()Benjamin Herrenschmidt
This is set to true when the index is for an instruction fetch translation. The core get_page_addr_code() sets it, as do the SOFTMMU_CODE_ACCESS acessors. All targets ignore it for now, and all other callers pass "false". This will allow targets who wish to split the mmu index between instruction and data accesses to do so. A subsequent patch will do just that for PowerPC. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Message-Id: <1439796853-4410-2-git-send-email-benh@kernel.crashing.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-08-24tcg: Remove tcg_gen_trunc_i64_i32Richard Henderson
Replacing it with tcg_gen_extrl_i64_i32. Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-08-24tcg: Split trunc_shr_i32 opcode into extr[lh]_i64_i32Richard Henderson
Rather than allow arbitrary shift+trunc, only concern ourselves with low and high parts. This is all that was being used anyway. Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-06-22disas: Remove uses of CPU envPeter Crosthwaite
disas does not need to access the CPU env for any reason. Change the APIs to accept CPU pointers instead. Small change pattern needs to be applied to all target translate.c. This brings us closer to making disas.o a common-obj and less architecture specific in general. Cc: Richard Henderson <rth@twiddle.net> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Eduardo Habkost <ehabkost@redhat.com> Cc: Michael Walle <michael@walle.cc> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Leon Alrae <leon.alrae@imgtec.com> Cc: Jia Liu <proljc@gmail.com> Cc: Alexander Graf <agraf@suse.de> Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> Cc: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Acked-by: Luiz Capitulino <lcapitulino@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2015-05-30target-tricore: fix BOL_ST_H_LONGOFF using ldBastian Koppelmann
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <1432289758-6250-4-git-send-email-kbastian@mail.uni-paderborn.de>
2015-05-30target-tricore: fix msub32_q producing the wrong overflow bitBastian Koppelmann
The inversion of the overflow bit as a special case, which was needed for the madd32_q instructions, does not apply for msub32_q instructions. So remove it. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <1432289758-6250-3-git-send-email-kbastian@mail.uni-paderborn.de>
2015-05-30target-tricore: fix OPC2_32_RR_DVINIT_HU having write before use on the resultBastian Koppelmann
If the argument r1 was the same as the extended result register r3+1, we would overwrite r1 and then use it. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-Id: <1432289758-6250-2-git-send-email-kbastian@mail.uni-paderborn.de>
2015-05-22target-tricore: add RR_DIV and RR_DIV_U instructions of the v1.6 ISABastian Koppelmann
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
2015-05-22target-tricore: add FRET instructions of the v1.6 ISABastian Koppelmann
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
2015-05-22target-tricore: add FCALL instructions of the v1.6 ISABastian Koppelmann
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
2015-05-22target-tricore: add SYS_RESTORE instruction of the v1.6 ISABastian Koppelmann
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
2015-05-22target-tricore: add RR_CRC32 instruction of the v1.6.1 ISABastian Koppelmann
This instruction was introduced by the new Aurix platform. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
2015-05-22target-tricore: add SWAPMSK instructions of the v1.6.1 ISABastian Koppelmann
Those instruction were introduced in the new Aurix platform. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
2015-05-22target-tricore: add CMPSWP instructions of the v1.6.1 ISABastian Koppelmann
Those instruction were introduced in the new Aurix platform. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
2015-05-22target-tricore: Add SRC_MOV_E instruction of the v1.6 ISABastian Koppelmann
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
2015-05-11target-tricore: fix SLR_LD_W and SLR_LD_W_POSTINC insn being a 2 byte memory ↵Bastian Koppelmann
access insted of 4 Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2015-05-11target-tricore: Fix LOOP using wrong register for compareBastian Koppelmann
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2015-03-30target-tricore: fix CACHEA/I_POSTINC/PREINC using data register..Bastian Koppelmann
..for address calculation instead address registers. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2015-03-24target-tricore: fix RRPW_DEXTR using wrong regBastian Koppelmann
RRPW_DEXTR used r1 for the low part and r2 for the high part. It should be the other way round. This also fixes that the result of the first shift was not saved in a temp and could overwrite registers that were needed for the second shift. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2015-03-24target-tricore: fix DVINIT_HU/BU calculating overflow before resultBastian Koppelmann
dvinit_hu/bu for ISA v1.3 calculate the higher part of the result, that is needed for the overflow bits, after calculating the overflow bits. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2015-03-19Fix typos in commentsViswesh
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Viswesh <visweshn92@gmail.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2015-03-16target-tricore: Add instructions of SYS opcode formatBastian Koppelmann
This adds only the non trap instructions. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2015-03-16target-tricore: Add instructions of RRRW opcode formatBastian Koppelmann
Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2015-03-16target-tricore: Add instructions of RRRR opcode formatBastian Koppelmann
Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2015-03-16target-tricore: Add instructions of RRR1 opcode format, which have 0xe3 as ↵Bastian Koppelmann
first opcode Add helpers helper_subadr_h/_ssov which subs one halfword and adds one halfword, rounds / and saturates each half word independently. Add microcode helper functions: * gen_msubad_h/ads_h: multiply two halfwords left justified and sub from the first one word and add the second one word / and saturate each resulting word independetly. * gen_msubadm_h/adms_h: multiply two halfwords in q-format left justified and sub from the first one word and add to the second one word / and saturate each resulting word independetly. * gen_msubadr32_h/32s_h: multiply two halfwords in q-format left justified and sub from the first one word and add to the second one word, round both results / and saturate each resulting word independetly. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2015-03-16target-tricore: Add instructions of RRR1 opcode format, which have 0x63 as ↵Bastian Koppelmann
first opcode Add helpers: * msub64_q_ssov: multiply two 32 bit q-format number, sub the result from a 64 bit q-format number and saturate. * msub32_q_sub_ssov: sub two 64 bit q-format numbers and return a 32 bit result. * msubr_q_ssov: multiply two 32 bit q-format numbers, sub the result from a 32 bit q-format number and saturate. * msubr_q: multiply two 32 bit q-format numbers and sub the result from a 32 bit q-format number. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2015-03-16target-tricore: Add instructions of RRR1 opcode format, which have 0xa3 as ↵Bastian Koppelmann
first opcode Add helpers: * sub64_ssov: subs two 64 bit values and saturates the result. * subr_h/_ssov: subs two halfwords from two words in q-format with rounding / and saturates each result independetly. Add microcode generator: * gen_sub64_d: adds two 64 bit values. * gen_msub_h/s_h: multiply four halfwords, sub each result left justfied from two word values / and saturate each result. * gen_msubm_h/s_h: multiply four halfwords, sub each result left justfied from two words values in q-format / and saturate each result. * gen_msubr32/64_h/s_h: multiply four halfwords, sub each result left justfied from two halftwords/words values in q-format / and saturate each result. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
generated by cgit v1.2.3 (git 2.26.2) at 2024-12-04 01:13:00 +0000