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path: root/target-tricore/translate.c
AgeCommit message (Expand)Author
2016-05-19cpu: move exec-all.h inclusion out of cpu.hPaolo Bonzini
2016-05-18Fix some typos found by codespellStefan Weil
2016-05-12tcg: Allow goto_tb to any target PC in user modeSergey Fedorov
2016-03-23target-tricore: Add ftoi and itof instructionsBastian Koppelmann
2016-03-23target-tricore: Add cmp.f instructionBastian Koppelmann
2016-03-23target-tricore: Add div.f instructionBastian Koppelmann
2016-03-23target-tricore: Add mul.f instructionBastian Koppelmann
2016-03-23target-tricore: add add.f/sub.f instructionsBastian Koppelmann
2016-03-23target-tricore: Move general CHECK_REG_PAIR of decode_rrr_divideBastian Koppelmann
2016-03-23target-tricore: Add FPU infrastructureBastian Koppelmann
2016-03-23target-tricore: add missing break in insn decode switch stmtBastian Koppelmann
2016-03-01tcg: Add type for vCPU pointersLluís Vilanova
2016-02-25target-tricore: add opd trap generationBastian Koppelmann
2016-02-25target-tricore: add illegal opcode trap generationBastian Koppelmann
2016-02-25target-tricore: Add trap handling & SOVF/OVF trapsBastian Koppelmann
2016-02-09tcg: Change tcg_global_mem_new_* to take a TCGv_ptrRichard Henderson
2016-02-03log: do not unnecessarily include qom/cpu.hPaolo Bonzini
2016-01-29tricore: Clean up includesPeter Maydell
2015-10-07tcg: Remove gen_intermediate_code_pcRichard Henderson
2015-10-07tcg: Pass data argument to restore_state_to_opcRichard Henderson
2015-10-07tcg: Add TCG_MAX_INSNSRichard Henderson
2015-10-07target-*: Increment num_insns immediately after tcg_gen_insn_startRichard Henderson
2015-10-07target-*: Unconditionally emit tcg_gen_insn_startRichard Henderson
2015-09-11tlb: Add "ifetch" argument to cpu_mmu_index()Benjamin Herrenschmidt
2015-08-24tcg: Remove tcg_gen_trunc_i64_i32Richard Henderson
2015-08-24tcg: Split trunc_shr_i32 opcode into extr[lh]_i64_i32Richard Henderson
2015-06-22disas: Remove uses of CPU envPeter Crosthwaite
2015-05-30target-tricore: fix BOL_ST_H_LONGOFF using ldBastian Koppelmann
2015-05-30target-tricore: fix msub32_q producing the wrong overflow bitBastian Koppelmann
2015-05-30target-tricore: fix OPC2_32_RR_DVINIT_HU having write before use on the resultBastian Koppelmann
2015-05-22target-tricore: add RR_DIV and RR_DIV_U instructions of the v1.6 ISABastian Koppelmann
2015-05-22target-tricore: add FRET instructions of the v1.6 ISABastian Koppelmann
2015-05-22target-tricore: add FCALL instructions of the v1.6 ISABastian Koppelmann
2015-05-22target-tricore: add SYS_RESTORE instruction of the v1.6 ISABastian Koppelmann
2015-05-22target-tricore: add RR_CRC32 instruction of the v1.6.1 ISABastian Koppelmann
2015-05-22target-tricore: add SWAPMSK instructions of the v1.6.1 ISABastian Koppelmann
2015-05-22target-tricore: add CMPSWP instructions of the v1.6.1 ISABastian Koppelmann
2015-05-22target-tricore: Add SRC_MOV_E instruction of the v1.6 ISABastian Koppelmann
2015-05-11target-tricore: fix SLR_LD_W and SLR_LD_W_POSTINC insn being a 2 byte memory ...Bastian Koppelmann
2015-05-11target-tricore: Fix LOOP using wrong register for compareBastian Koppelmann
2015-03-30target-tricore: fix CACHEA/I_POSTINC/PREINC using data register..Bastian Koppelmann
2015-03-24target-tricore: fix RRPW_DEXTR using wrong regBastian Koppelmann
2015-03-24target-tricore: fix DVINIT_HU/BU calculating overflow before resultBastian Koppelmann
2015-03-19Fix typos in commentsViswesh
2015-03-16target-tricore: Add instructions of SYS opcode formatBastian Koppelmann
2015-03-16target-tricore: Add instructions of RRRW opcode formatBastian Koppelmann
2015-03-16target-tricore: Add instructions of RRRR opcode formatBastian Koppelmann
2015-03-16target-tricore: Add instructions of RRR1 opcode format, which have 0xe3 as fi...Bastian Koppelmann
2015-03-16target-tricore: Add instructions of RRR1 opcode format, which have 0x63 as fi...Bastian Koppelmann
2015-03-16target-tricore: Add instructions of RRR1 opcode format, which have 0xa3 as fi...Bastian Koppelmann
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