| Age | Commit message (Expand) | Author |
|---|
| 2015-05-30 | target-tricore: fix BOL_ST_H_LONGOFF using ld | Bastian Koppelmann |
| 2015-05-30 | target-tricore: fix msub32_q producing the wrong overflow bit | Bastian Koppelmann |
| 2015-05-30 | target-tricore: fix OPC2_32_RR_DVINIT_HU having write before use on the result | Bastian Koppelmann |
| 2015-05-22 | target-tricore: add RR_DIV and RR_DIV_U instructions of the v1.6 ISA | Bastian Koppelmann |
| 2015-05-22 | target-tricore: add FRET instructions of the v1.6 ISA | Bastian Koppelmann |
| 2015-05-22 | target-tricore: add FCALL instructions of the v1.6 ISA | Bastian Koppelmann |
| 2015-05-22 | target-tricore: add SYS_RESTORE instruction of the v1.6 ISA | Bastian Koppelmann |
| 2015-05-22 | target-tricore: add RR_CRC32 instruction of the v1.6.1 ISA | Bastian Koppelmann |
| 2015-05-22 | target-tricore: add SWAPMSK instructions of the v1.6.1 ISA | Bastian Koppelmann |
| 2015-05-22 | target-tricore: add CMPSWP instructions of the v1.6.1 ISA | Bastian Koppelmann |
| 2015-05-22 | target-tricore: Add SRC_MOV_E instruction of the v1.6 ISA | Bastian Koppelmann |
| 2015-05-11 | target-tricore: fix SLR_LD_W and SLR_LD_W_POSTINC insn being a 2 byte memory ... | Bastian Koppelmann |
| 2015-05-11 | target-tricore: Fix LOOP using wrong register for compare | Bastian Koppelmann |
| 2015-03-30 | target-tricore: fix CACHEA/I_POSTINC/PREINC using data register.. | Bastian Koppelmann |
| 2015-03-24 | target-tricore: fix RRPW_DEXTR using wrong reg | Bastian Koppelmann |
| 2015-03-24 | target-tricore: fix DVINIT_HU/BU calculating overflow before result | Bastian Koppelmann |
| 2015-03-19 | Fix typos in comments | Viswesh |
| 2015-03-16 | target-tricore: Add instructions of SYS opcode format | Bastian Koppelmann |
| 2015-03-16 | target-tricore: Add instructions of RRRW opcode format | Bastian Koppelmann |
| 2015-03-16 | target-tricore: Add instructions of RRRR opcode format | Bastian Koppelmann |
| 2015-03-16 | target-tricore: Add instructions of RRR1 opcode format, which have 0xe3 as fi... | Bastian Koppelmann |
| 2015-03-16 | target-tricore: Add instructions of RRR1 opcode format, which have 0x63 as fi... | Bastian Koppelmann |
| 2015-03-16 | target-tricore: Add instructions of RRR1 opcode format, which have 0xa3 as fi... | Bastian Koppelmann |
| 2015-03-13 | tcg: Change translator-side labels to a pointer | Richard Henderson |
| 2015-03-03 | target-tricore: Add instructions of RRR1 opcode format, which have 0xc3 as fi... | Bastian Koppelmann |
| 2015-03-03 | target-tricore: Add instructions of RRR1 opcode format, which have 0x43 as fi... | Bastian Koppelmann |
| 2015-03-03 | target-tricore: Add instructions of RRR1 opcode format, which have 0x83 as fi... | Bastian Koppelmann |
| 2015-03-03 | target-tricore: Add instructions of RRR2 opcode format | Bastian Koppelmann |
| 2015-03-03 | target-tricore: Fix RLC_ADDI, RLC_ADDIH using wrong microcode helper | Bastian Koppelmann |
| 2015-02-12 | tcg: Introduce tcg_op_buf_count and tcg_op_buf_full | Richard Henderson |
| 2015-02-12 | tcg: Move emit of INDEX_op_end into gen_tb_end | Richard Henderson |
| 2015-01-27 | target-tricore: Add instructions of RRR opcode format | Bastian Koppelmann |
| 2015-01-27 | target-tricore: Add instructions of RRPW opcode format | Bastian Koppelmann |
| 2015-01-27 | target-tricore: Add instructions of RR2 opcode format | Bastian Koppelmann |
| 2015-01-27 | target-tricore: Add instructions of RR1 opcode format, that have 0x93 as firs... | Bastian Koppelmann |
| 2015-01-26 | target-tricore: Fix bugs found by coverity | Bastian Koppelmann |
| 2015-01-26 | target-tricore: Several translator and cpu model fixes | Bastian Koppelmann |
| 2015-01-15 | target-tricore: Fix new typos | Stefan Weil |
| 2015-01-09 | Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging | Peter Maydell |
| 2015-01-03 | gen-icount: check cflags instead of use_icount global | Paolo Bonzini |
| 2014-12-21 | target-tricore: Add instructions of RR1 opcode format, that have 0xb3 as firs... | Bastian Koppelmann |
| 2014-12-21 | target-tricore: Fix MFCR/MTCR insn and B format offset. | Bastian Koppelmann |
| 2014-12-21 | target-tricore: Add missing 1.6 insn of BOL opcode format | Bastian Koppelmann |
| 2014-12-21 | target-tricore: Add instructions of RR opcode format, that have 0x4b as the f... | Bastian Koppelmann |
| 2014-12-21 | target-tricore: Add instructions of RR opcode format, that have 0x1 as the fi... | Bastian Koppelmann |
| 2014-12-21 | target-tricore: Add instructions of RR opcode format, that have 0xf as the fi... | Bastian Koppelmann |
| 2014-12-21 | target-tricore: Add instructions of RR opcode format, that have 0xb as the fi... | Bastian Koppelmann |
| 2014-12-21 | target-tricore: Fix mask handling JNZ.T being 7 bit long | Bastian Koppelmann |
| 2014-12-21 | target-tricore: pretty-print register dump and show more status registers | Alex Zuepke |
| 2014-12-21 | target-tricore: add missing 64-bit MOV in RLC format | Alex Zuepke |
