| Age | Commit message (Expand) | Author |
|---|
| 2015-05-22 | target-tricore: add RR_DIV and RR_DIV_U instructions of the v1.6 ISA | Bastian Koppelmann |
| 2015-05-22 | target-tricore: add RR_CRC32 instruction of the v1.6.1 ISA | Bastian Koppelmann |
| 2015-05-11 | target-tricore: fix rfe not restoring the PC | Bastian Koppelmann |
| 2015-05-11 | target-tricore: fix rslcx restoring the upper context instead of the lower | Bastian Koppelmann |
| 2015-04-04 | target-tricore: Fix check which was always false | Stefan Weil |
| 2015-03-24 | target-tricore: properly fix dvinit_b/h_13 | Bastian Koppelmann |
| 2015-03-24 | target-tricore: Fix two helper functions (clang warnings) | Stefan Weil |
| 2015-03-16 | target-tricore: Add instructions of SYS opcode format | Bastian Koppelmann |
| 2015-03-16 | target-tricore: Add instructions of RRR1 opcode format, which have 0xe3 as fi... | Bastian Koppelmann |
| 2015-03-16 | target-tricore: Add instructions of RRR1 opcode format, which have 0x63 as fi... | Bastian Koppelmann |
| 2015-03-16 | target-tricore: Add instructions of RRR1 opcode format, which have 0xa3 as fi... | Bastian Koppelmann |
| 2015-03-03 | target-tricore: Add instructions of RRR1 opcode format, which have 0xc3 as fi... | Bastian Koppelmann |
| 2015-03-03 | target-tricore: Add instructions of RRR1 opcode format, which have 0x43 as fi... | Bastian Koppelmann |
| 2015-03-03 | target-tricore: Add instructions of RRR1 opcode format, which have 0x83 as fi... | Bastian Koppelmann |
| 2015-03-03 | target-tricore: fix msub32_suov return wrong results | Bastian Koppelmann |
| 2015-01-27 | target-tricore: Add instructions of RRR opcode format | Bastian Koppelmann |
| 2015-01-26 | target-tricore: split up suov32 into suov32_pos and suov32_neg | Bastian Koppelmann |
| 2015-01-26 | target-tricore: calculate av bits before saturation | Bastian Koppelmann |
| 2015-01-26 | target-tricore: Several translator and cpu model fixes | Bastian Koppelmann |
| 2015-01-26 | target-tricore: Add missing ULL suffix on 64 bit constant | Peter Maydell |
| 2014-12-21 | target-tricore: Add instructions of RR1 opcode format, that have 0xb3 as firs... | Bastian Koppelmann |
| 2014-12-21 | target-tricore: Add instructions of RR opcode format, that have 0x4b as the f... | Bastian Koppelmann |
| 2014-12-21 | target-tricore: Add instructions of RR opcode format, that have 0xf as the fi... | Bastian Koppelmann |
| 2014-12-21 | target-tricore: Add instructions of RR opcode format, that have 0xb as the fi... | Bastian Koppelmann |
| 2014-12-21 | target-tricore: Change SSOV/SUOV makro name to SSOV32/SUOV32 | Bastian Koppelmann |
| 2014-12-10 | target-tricore: Add instructions of RCR opcode format | Bastian Koppelmann |
| 2014-12-10 | target-tricore: Add instructions of RLC opcode format | Bastian Koppelmann |
| 2014-12-10 | target-tricore: Add instructions of RC opcode format | Bastian Koppelmann |
| 2014-10-20 | target-tricore: Add instructions of BO opcode format | Bastian Koppelmann |
| 2014-10-20 | target-tricore: Add instructions of ABS, ABSB opcode format | Bastian Koppelmann |
| 2014-10-20 | target-tricore: Cleanup and Bugfixes | Bastian Koppelmann |
| 2014-09-01 | target-tricore: Add instructions of SR opcode format | Bastian Koppelmann |
| 2014-09-01 | target-tricore: Add instructions of SC opcode format | Bastian Koppelmann |
| 2014-09-01 | target-tricore: Add instructions of SB opcode format | Bastian Koppelmann |
| 2014-09-01 | target-tricore: Add instructions of SRR opcode format | Bastian Koppelmann |
| 2014-09-01 | target-tricore: Add softmmu support | Bastian Koppelmann |
| 2014-09-01 | target-tricore: Add target stubs and qom-cpu | Bastian Koppelmann |
