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2015-10-07tcg: Remove gen_intermediate_code_pcRichard Henderson
2015-10-07tcg: Pass data argument to restore_state_to_opcRichard Henderson
2015-10-07tcg: Add TCG_MAX_INSNSRichard Henderson
2015-10-07target-*: Drop cpu_gen_code defineRichard Henderson
2015-10-07target-*: Increment num_insns immediately after tcg_gen_insn_startRichard Henderson
2015-10-07target-*: Unconditionally emit tcg_gen_insn_startRichard Henderson
2015-10-07tcg: Rename debug_insn_start to insn_startRichard Henderson
2015-09-15target-tilegx: Handle v1shl, v1shru, v1shrsRichard Henderson
2015-09-15target-tilegx: Handle v1shli, v1shruiRichard Henderson
2015-09-15target-tilegx: Handle v4int_l/hRichard Henderson
2015-09-15target-tilegx: Handle atomic instructionsRichard Henderson
2015-09-15target-tilegx: Handle mtspr, mfsprRichard Henderson
2015-09-15target-tilegx: Handle v1cmpeq, v1cmpneRichard Henderson
2015-09-15target-tilegx: Handle mask instructionsRichard Henderson
2015-09-15target-tilegx: Handle scalar multiply instructionsRichard Henderson
2015-09-15target-tilegx: Handle conditional move instructionsRichard Henderson
2015-09-15target-tilegx: Handle shift instructionsRichard Henderson
2015-09-15target-tilegx: Handle bitfield instructionsRichard Henderson
2015-09-15target-tilegx: Implement system and memory management instructionsRichard Henderson
2015-09-15target-tilegx: Handle comparison instructionsRichard Henderson
2015-09-15target-tilegx: Handle conditional branch instructionsRichard Henderson
2015-09-15target-tilegx: Handle unconditional jump instructionsRichard Henderson
2015-09-15target-tilegx: Handle post-increment load and store instructionsRichard Henderson
2015-09-15target-tilegx: Handle basic load and store instructionsRichard Henderson
2015-09-15target-tilegx: Handle most bit manipulation instructionsRichard Henderson
2015-09-15target-tilegx: Handle arithmetic instructionsRichard Henderson
2015-09-15target-tilegx: Handle simple logical operationsRichard Henderson
2015-09-15target-tilegx: Add TILE-Gx building filesChen Gang
2015-09-15target-tilegx: Generate SEGV properlyRichard Henderson
2015-09-15target-tilegx: Framework for decoding bundlesRichard Henderson
2015-09-15target-tilegx: Add several helpers for instructions translationChen Gang
2015-09-15target-tilegx: Add cpu basic features for linux-userChen Gang
2015-09-15target-tilegx: Add special register information from Tilera CorporationChen Gang
2015-09-15target-tilegx: Fix LDNA_ADD_IMM8_OPCODE_X1Richard Henderson
2015-09-15target-tilegx: Modify _SPECIAL_ opcodesRichard Henderson
2015-09-15target-tilegx: Modify opcode_tilegx.h to fit QEMU usageChen Gang
2015-09-15target-tilegx: Add opcode basic implementation from Tilera CorporationChen Gang