Age | Commit message (Expand) | Author |
2016-06-29 | target-*: Don't redefine cpu_exec() | Peter Crosthwaite |
2016-06-20 | exec: [tcg] Track which vCPU is performing translation and execution | Lluís Vilanova |
2016-05-19 | cpu: move exec-all.h inclusion out of cpu.h | Paolo Bonzini |
2016-05-12 | tb: consistently use uint32_t for tb->flags | Emilio G. Cota |
2016-03-22 | include/qemu/osdep.h: Don't include qapi/error.h | Markus Armbruster |
2016-03-01 | tcg: Add type for vCPU pointers | Lluís Vilanova |
2016-02-23 | all: Clean up includes | Peter Maydell |
2016-02-09 | tcg: Change tcg_global_mem_new_* to take a TCGv_ptr | Richard Henderson |
2016-02-03 | log: do not unnecessarily include qom/cpu.h | Paolo Bonzini |
2016-01-29 | tilegx: Clean up includes | Peter Maydell |
2015-10-22 | target-tilegx: Implement prefetch instructions in pipe y2 | Chen Gang |
2015-10-09 | qdev: Protect device-list-properties against broken devices | Markus Armbruster |
2015-10-08 | Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20151007' into staging | Peter Maydell |
2015-10-07 | tcg: Remove gen_intermediate_code_pc | Richard Henderson |
2015-10-07 | tcg: Pass data argument to restore_state_to_opc | Richard Henderson |
2015-10-07 | tcg: Add TCG_MAX_INSNS | Richard Henderson |
2015-10-07 | target-*: Drop cpu_gen_code define | Richard Henderson |
2015-10-07 | target-*: Increment num_insns immediately after tcg_gen_insn_start | Richard Henderson |
2015-10-07 | target-*: Unconditionally emit tcg_gen_insn_start | Richard Henderson |
2015-10-07 | tcg: Rename debug_insn_start to insn_start | Richard Henderson |
2015-10-07 | target-tilegx: Support iret instruction and related special registers | Chen Gang |
2015-10-07 | target-tilegx: Use TILEGX_EXCP_OPCODE_UNKNOWN and TILEGX_EXCP_OPCODE_UNIMPLEM... | Chen Gang |
2015-10-07 | target-tilegx: Implement v2mults instruction | Chen Gang |
2015-10-07 | target-tilegx: Implement v?int_* instructions. | Chen Gang |
2015-10-07 | target-tilegx: Implement v2sh* instructions | Chen Gang |
2015-10-07 | target-tilegx: Handle nofault prefetch instructions | Richard Henderson |
2015-10-07 | target-tilegx: Fix a typo for mnemonic about "ld_add" | Chen Gang |
2015-10-07 | target-tilegx: Use TILEGX_EXCP_SIGNAL instead of TILEGX_EXCP_SEGV | Richard Henderson |
2015-10-07 | target-tilegx: Decode ill pseudo-instructions | Chen Gang |
2015-10-07 | target-tilegx: Let x1 pipe process bpt instruction only | Chen Gang |
2015-10-07 | target-tilegx: Implement complex multiply instructions | Richard Henderson |
2015-10-07 | target-tilegx: Implement table index instructions | Richard Henderson |
2015-10-07 | target-tilegx: Implement crc instructions | Richard Henderson |
2015-10-07 | target-tilegx: Implement v1multu instruction | Chen Gang |
2015-10-07 | target-tilegx: Implement v*add and v*sub instructions | Chen Gang |
2015-10-07 | target-tilegx: Implement v*shl, v*shru, and v*shrs instructions | Chen Gang |
2015-10-07 | target-tilegx: Tidy simd_helper.c | Richard Henderson |
2015-09-15 | target-tilegx: Handle v1shl, v1shru, v1shrs | Richard Henderson |
2015-09-15 | target-tilegx: Handle v1shli, v1shrui | Richard Henderson |
2015-09-15 | target-tilegx: Handle v4int_l/h | Richard Henderson |
2015-09-15 | target-tilegx: Handle atomic instructions | Richard Henderson |
2015-09-15 | target-tilegx: Handle mtspr, mfspr | Richard Henderson |
2015-09-15 | target-tilegx: Handle v1cmpeq, v1cmpne | Richard Henderson |
2015-09-15 | target-tilegx: Handle mask instructions | Richard Henderson |
2015-09-15 | target-tilegx: Handle scalar multiply instructions | Richard Henderson |
2015-09-15 | target-tilegx: Handle conditional move instructions | Richard Henderson |
2015-09-15 | target-tilegx: Handle shift instructions | Richard Henderson |
2015-09-15 | target-tilegx: Handle bitfield instructions | Richard Henderson |
2015-09-15 | target-tilegx: Implement system and memory management instructions | Richard Henderson |
2015-09-15 | target-tilegx: Handle comparison instructions | Richard Henderson |