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2015-10-07target-tilegx: Use TILEGX_EXCP_SIGNAL instead of TILEGX_EXCP_SEGVRichard Henderson
Consolidate signal handling under a single exception. Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07target-tilegx: Decode ill pseudo-instructionsChen Gang
Notice raise and bpt, decoding the constants embedded in the nop addil instruction in the x0 slot. [rth: Generalize TILEGX_EXCP_OPCODE_ILL to TILEGX_EXCP_SIGNAL. Drop validation of signal values.] Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> Message-Id: <1443243635-4886-1-git-send-email-gang.chen.5i5j@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07target-tilegx: Let x1 pipe process bpt instruction onlyChen Gang
According to the related document, bpt can be only in x1 pipe. Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> Message-Id: <1443224574-2718-1-git-send-email-gang.chen.5i5j@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07target-tilegx: Implement complex multiply instructionsRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07target-tilegx: Implement table index instructionsRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07target-tilegx: Implement crc instructionsRichard Henderson
Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07target-tilegx: Implement v1multu instructionChen Gang
Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-Id: <1442874414-3578-1-git-send-email-gang.chen.5i5j@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07target-tilegx: Implement v*add and v*sub instructionsChen Gang
[rth: Implement everything inline; handle v1addi and v2addi as well.] Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> Message-Id: <1442873918-3394-1-git-send-email-gang.chen.5i5j@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07target-tilegx: Implement v*shl, v*shru, and v*shrs instructionsChen Gang
v2sh* are implemented with helper functions; v4sh* are implmeneted with inline code. Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> Message-Id: <1442872055-2836-1-git-send-email-gang.chen.5i5j@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07target-tilegx: Tidy simd_helper.cRichard Henderson
Using the V1 macro when we want to replicate a byte across the 8 elements of the word. Using deposit and extract for manipulating specific elements. Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-15target-tilegx: Handle v1shl, v1shru, v1shrsRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-15target-tilegx: Handle v1shli, v1shruiRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-15target-tilegx: Handle v4int_l/hRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-15target-tilegx: Handle atomic instructionsRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-15target-tilegx: Handle mtspr, mfsprRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-15target-tilegx: Handle v1cmpeq, v1cmpneRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-15target-tilegx: Handle mask instructionsRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-15target-tilegx: Handle scalar multiply instructionsRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-15target-tilegx: Handle conditional move instructionsRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-15target-tilegx: Handle shift instructionsRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-15target-tilegx: Handle bitfield instructionsRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-15target-tilegx: Implement system and memory management instructionsRichard Henderson
Most of which are either nops or exceptions. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-15target-tilegx: Handle comparison instructionsRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-15target-tilegx: Handle conditional branch instructionsRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-15target-tilegx: Handle unconditional jump instructionsRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-15target-tilegx: Handle post-increment load and store instructionsRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-15target-tilegx: Handle basic load and store instructionsRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-15target-tilegx: Handle most bit manipulation instructionsRichard Henderson
The crc instructions are omitted from this set. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-15target-tilegx: Handle arithmetic instructionsRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-15target-tilegx: Handle simple logical operationsRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-15target-tilegx: Add TILE-Gx building filesChen Gang
Add related configuration and make files for tilegx. The target can now build, though not run anything. Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <BLU436-SMTP1588E5A03AD5E94B07E988B9660@phx.gbl> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-15target-tilegx: Generate SEGV properlyRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-15target-tilegx: Framework for decoding bundlesRichard Henderson
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-15target-tilegx: Add several helpers for instructions translationChen Gang
The related instructions are exception, cntlz, cnttz, shufflebytes. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> Message-Id: <BLU436-SMTP83F96FD8422BE49AFDC9DFB9660@phx.gbl> [rth: Remove incorrect implementation of add_saturate.] Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-15target-tilegx: Add cpu basic features for linux-userChen Gang
It implements minimized cpu features for linux-user. Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <BLU436-SMTP114819BB03D853801AA9C3CB9660@phx.gbl> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-15target-tilegx: Add special register information from Tilera CorporationChen Gang
The related copy is from Linux kernel "arch/tile/include/uapi/arch/ spr_def_64.h". Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <BLU436-SMTP1093D605AAE9B4837B564B8B9660@phx.gbl> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-15target-tilegx: Fix LDNA_ADD_IMM8_OPCODE_X1Richard Henderson
An obvious typo in the mnemonic here. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-15target-tilegx: Modify _SPECIAL_ opcodesRichard Henderson
Both ADDX_SPECIAL_0_OPCODE_Y1 and ADD_SPECIAL_0_OPCODE_Y1 do not appear to be "special" in any way, except that they don't follow the normal naming convention using _RRR_. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-15target-tilegx: Modify opcode_tilegx.h to fit QEMU usageChen Gang
Use 'inline' instead of '__inline', and also use 'uint64_t' instead of "unsigned long long" Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <BLU436-SMTP1945B04384351D5EE7D9DECB9660@phx.gbl> Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-09-15target-tilegx: Add opcode basic implementation from Tilera CorporationChen Gang
It is copied from Linux kernel "arch/tile/include/uapi/arch/ opcode_tilegx.h". Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <BLU436-SMTP2087FA98B64A20B25155D9AB9660@phx.gbl> Signed-off-by: Richard Henderson <rth@twiddle.net>
generated by cgit v1.2.3 (git 2.26.2) at 2025-01-01 04:11:53 +0000