aboutsummaryrefslogtreecommitdiff
path: root/target-tilegx/translate.c
AgeCommit message (Expand)Author
2016-02-09tcg: Change tcg_global_mem_new_* to take a TCGv_ptrRichard Henderson
2016-02-03log: do not unnecessarily include qom/cpu.hPaolo Bonzini
2016-01-29tilegx: Clean up includesPeter Maydell
2015-10-22target-tilegx: Implement prefetch instructions in pipe y2Chen Gang
2015-10-08Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20151007' into stagingPeter Maydell
2015-10-07tcg: Remove gen_intermediate_code_pcRichard Henderson
2015-10-07tcg: Pass data argument to restore_state_to_opcRichard Henderson
2015-10-07tcg: Add TCG_MAX_INSNSRichard Henderson
2015-10-07target-*: Increment num_insns immediately after tcg_gen_insn_startRichard Henderson
2015-10-07target-*: Unconditionally emit tcg_gen_insn_startRichard Henderson
2015-10-07tcg: Rename debug_insn_start to insn_startRichard Henderson
2015-10-07target-tilegx: Support iret instruction and related special registersChen Gang
2015-10-07target-tilegx: Use TILEGX_EXCP_OPCODE_UNKNOWN and TILEGX_EXCP_OPCODE_UNIMPLEM...Chen Gang
2015-10-07target-tilegx: Implement v2mults instructionChen Gang
2015-10-07target-tilegx: Implement v?int_* instructions.Chen Gang
2015-10-07target-tilegx: Implement v2sh* instructionsChen Gang
2015-10-07target-tilegx: Handle nofault prefetch instructionsRichard Henderson
2015-10-07target-tilegx: Fix a typo for mnemonic about "ld_add"Chen Gang
2015-10-07target-tilegx: Decode ill pseudo-instructionsChen Gang
2015-10-07target-tilegx: Let x1 pipe process bpt instruction onlyChen Gang
2015-10-07target-tilegx: Implement complex multiply instructionsRichard Henderson
2015-10-07target-tilegx: Implement table index instructionsRichard Henderson
2015-10-07target-tilegx: Implement crc instructionsRichard Henderson
2015-10-07target-tilegx: Implement v1multu instructionChen Gang
2015-10-07target-tilegx: Implement v*add and v*sub instructionsChen Gang
2015-10-07target-tilegx: Implement v*shl, v*shru, and v*shrs instructionsChen Gang
2015-09-15target-tilegx: Handle v1shl, v1shru, v1shrsRichard Henderson
2015-09-15target-tilegx: Handle v1shli, v1shruiRichard Henderson
2015-09-15target-tilegx: Handle v4int_l/hRichard Henderson
2015-09-15target-tilegx: Handle atomic instructionsRichard Henderson
2015-09-15target-tilegx: Handle mtspr, mfsprRichard Henderson
2015-09-15target-tilegx: Handle v1cmpeq, v1cmpneRichard Henderson
2015-09-15target-tilegx: Handle mask instructionsRichard Henderson
2015-09-15target-tilegx: Handle scalar multiply instructionsRichard Henderson
2015-09-15target-tilegx: Handle conditional move instructionsRichard Henderson
2015-09-15target-tilegx: Handle shift instructionsRichard Henderson
2015-09-15target-tilegx: Handle bitfield instructionsRichard Henderson
2015-09-15target-tilegx: Implement system and memory management instructionsRichard Henderson
2015-09-15target-tilegx: Handle comparison instructionsRichard Henderson
2015-09-15target-tilegx: Handle conditional branch instructionsRichard Henderson
2015-09-15target-tilegx: Handle unconditional jump instructionsRichard Henderson
2015-09-15target-tilegx: Handle post-increment load and store instructionsRichard Henderson
2015-09-15target-tilegx: Handle basic load and store instructionsRichard Henderson
2015-09-15target-tilegx: Handle most bit manipulation instructionsRichard Henderson
2015-09-15target-tilegx: Handle arithmetic instructionsRichard Henderson
2015-09-15target-tilegx: Handle simple logical operationsRichard Henderson
2015-09-15target-tilegx: Framework for decoding bundlesRichard Henderson
generated by cgit v1.2.3 (git 2.26.2) at 2024-12-27 02:23:24 +0000