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2009-08-24cleanup cpu-exec.c, part 0/N: consolidate handle_cpu_signalNathan Froyd
handle_cpu_signal is very nearly copy-paste code for each target, with a few minor variations. This patch sets up appropriate defaults for a generic handle_cpu_signal and provides overrides for particular targets that did things differently. Fixing things like the persistent (XXX: use sigsetjmp) should now become somewhat easier. Previous comments on this patch suggest that the "activate soft MMU for this block" comments refer to defunct functionality. I have removed such blocks for the appropriate targets in this patch. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-08-22sparc32 remove an unnecessary cpu irq setBlue Swirl
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-08-22Sparc32/64: fix jmpl followed by branchBlue Swirl
Fix a case where 'jmpl' instruction followed by a branch instruction was handled incorrectly. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-08-18Sparc32/64: Fix user emulator breakageBlue Swirl
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-08-15Fix desynchronization of condition code state when a memory access trapsBlue Swirl
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-08-04Sparc64: replace tsptr with helper routineIgor Kovalenko
tl and tsptr of members sparc64 cpu state must be changed simultaneously to keep trap state window in sync with current trap level. Currently translation of store to tl does not change tsptr, which leads to corrupt trap state on corresponding trap level. This patch removes tsptr from sparc64 cpu state and replaces all uses with call to helper routine. Changes v0->v1: - reimplemented helper routine with tcg generator - on cpu reset trap type and pstate are populated with power-on reset values, including tl=maxtl Signed-off-by: igor.v.kovalenko@gmail.com Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-07-31sparc64 flush pending conditional evaluations before exposing cpu stateIgor Kovalenko
If translation block is interrupted by e.g. mmu exception we need to compute conditional flags for inclusion into saved cpu state. Otherwise after return from trap conditional instructions would use stale psr/xcc data. Signed-off-by: igor.v.kovalenko@gmail.com -- Kind regards, Igor V. Kovalenko
2009-07-27rename WORDS_BIGENDIAN to HOST_WORDS_BIGENDIANJuan Quintela
Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-07-27sparc64 really implement itlb/dtlb automatic replacement writesIgor Kovalenko
- implement "used" bit in tlb translation entry - mark tlb entry used if qemu code/data translation succeeds - fold i/d mmu replacement writes code into replace_tlb_1bit_lru which adds 1bit lru replacement algorithm; previously code tried to replace first unlocked entry only - extract more bitmasks to named macros - add "immu" or "dmmu" type name to debugging output where appropriate Signed-off-by: igor.v.kovalenko@gmail.com -- Kind regards, Igor V. Kovalenko
2009-07-27sparc64 name mmu registers and general cleanupIgor Kovalenko
- add names to mmu registers, this helps understanding the code which uses/modifies them. - fold i/d mmu tlb entries tag and tte arrays into arrays of tlb entries - extract demap_tlb routine (code duplication) - extract replace_tlb routine (code duplication) - flush qemu tlb translations when replacing sparc64 mmu tlb entries I have no test case which demands flushing qemu translations, and this patch should have no other visible changes to runtime. Signed-off-by: igor.v.kovalenko@gmail.com -- Kind regards, Igor V. Kovalenko
2009-07-20Fix most warnings (errors with -Werror) when debugging is enabledBlue Swirl
I used the following command to enable debugging: perl -p -i -e 's/^\/\/#define DEBUG/#define DEBUG/g' * */* */*/* Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-07-16Update to a hopefully more future proof FSF addressBlue Swirl
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-07-12sparc64: trap handling correctionsIgor Kovalenko
On Sun, Jul 12, 2009 at 12:09 PM, Blue Swirl<blauwirbel@gmail.com> wrote: > On 7/12/09, Igor Kovalenko <igor.v.kovalenko@gmail.com> wrote: >> Good trap handling is required to process interrupts. >>  This patch fixes the following: >> >>  - sparc64 has no wim register >>  - sparc64 has no psret register, use IE bit of pstate >>   extract IE checking code to cpu_interrupts_enabled >>  - alternate globals are not available if cpu has GL feature >>   in this case bit AG of pstate is constant zero >>  - write to pstate must actually write pstate >>   even if cpu has GL feature >> >>  Also timer interrupt is handled using do_interrupt. > > A bit too much for one patch. Please also remove the code instead of > commenting out. I now excluded timer interrupt related part. To my mind other changes are essentially tied together. > PUT_PSR for Sparc64 needs CC_OP = CC_OP_FLAGS; like Sparc32. Fixed, please find attached the updated version. -- Kind regards, Igor V. Kovalenko
2009-07-12sparc64: fix helper_st_asi little endian case typoIgor Kovalenko
On Sun, Jul 12, 2009 at 12:43 AM, Stuart Brady<sdbrady@ntlworld.com> wrote: > On Sat, Jul 11, 2009 at 10:22:18PM +0400, Igor Kovalenko wrote: >> It is clear that intention is to byte-swap value to be written, not >> the target address. > > @@ -1949,13 +1949,13 @@ void helper_st_asi(target_ulong addr, ta >     case 0x89: // Secondary LE >         switch(size) { >         case 2: > -            addr = bswap16(addr); > +            addr = bswap16(val); >             ^^^^ > Shouldn't that be 'val = bswap16(val)' (and likewise for the 32-bit and > 64-bit cases)?  Also needs a 'signed-off-by:'... > > Cheers, > -- > Stuart Brady > Thanks, that part I did not runtime-tested. Not sure if those asi stores are of any use for user-mode emulator. Please find attached the corrected version. Signed-off-by: igor.v.kovalenko@gmail.com -- Kind regards, Igor V. Kovalenko
2009-07-12sparc64: unify mmu tag matching codeIgor Kovalenko
This patch extracts common part of sparc64 tag matching code used by IMMU and DMMU lookups. Signed-off-by: igor.v.kovalenko@gmail.com -- Kind regards, Igor V. Kovalenko
2009-07-12sparc64: mmu bypass mode correctionIgor Kovalenko
This Implement physical address truncation in mmu bypass mode. IMMU bypass is also active when cpu enters RED_STATE Signed-off-by: igor.v.kovalenko@gmail.com -- Kind regards, Igor V. Kovalenko
2009-06-06Use correct type for SPARC cpu_cc_opPaul Brook
Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-05-21Convert machine registration to use module init functionsAnthony Liguori
This cleans up quite a lot of #ifdefs, extern variables, and other ugliness. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-05-19Hardware convenience libraryPaul Brook
The only target dependency for most hardware is sizeof(target_phys_addr_t). Build these files into a convenience library, and use that instead of building for every target. Remove and poison various target specific macros to avoid bogus target dependencies creeping back in. Big/Little endian is not handled because devices should not know or care about this to start with. Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-05-13Include assert.h from qemu-common.hPaul Brook
Include assert.h from qemu-common.h and remove other direct uses. cpu-all.h still need to include it because of the dyngen-exec.h hacks Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-05-13Replace gcc variadic macro extension with C99 versionBlue Swirl
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-05-10Convert mulsccBlue Swirl
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-05-10Convert udiv/sdivBlue Swirl
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-05-10Convert tagged opsBlue Swirl
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-05-10Convert subxBlue Swirl
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-05-10Convert subBlue Swirl
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-05-10Convert logical operations and umul/smulBlue Swirl
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-05-10Convert addxBlue Swirl
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-05-10Convert addBlue Swirl
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-05-10Use dynamical computation for condition codesBlue Swirl
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-05-03Optimize cmp x, 0 caseBlue Swirl
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-05-03ReindentBlue Swirl
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-05-02Improve instruction name comments for easier searchingBlue Swirl
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-05-02Clarify: dmmuregs[1] is not a typoBlue Swirl
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-05-02Optimize operations with immediate parametersBlue Swirl
2009-05-02Fix Sparc64 sign extension problemsBlue Swirl
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-04-28sparc64 fix context value for ITLB faultIgor Kovalenko
Revert previous change to get_physical_address_code: I/D MMU context register is shared, so using dmmuregs[1] is correct Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
2009-04-27sparc64 fix TLB match codeIgor Kovalenko
TLB match code must respect page size, otherwise 4M page mappings may be not found. Also correct a typo in get_physical_address_code which should use IMMU registers. Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com> -- Kind regards, Igor V. Kovalenko
2009-04-25Fix a warning in sparc64-linux-user buildBlue Swirl
2009-04-25sparc64 support TSB related MMU registersIgor Kovalenko
Posting updated patch to the list... >>> On Fri, Apr 24, 2009 at 9:42 PM, Blue Swirl <blauwirbel@gmail.com> wrote: >>>  > >>>  > Nice, though I didn't notice any visible improvement in my tests. >>> >>> This early in boot process there is not much to output; and I test >>>  recent kernel which may use different startup sequence. >>>  I modified openbios cif handler to output arguments and I now can see >>>  visible difference. >>> >>> >>>  > >>>  > About the patch, there are a few problems: >>>  > - it breaks Sparc32 >>> >>> You mean it stops working? >> >> Does not even build. Fixed now. >>>  > - commented out code is ugly >>>  > - if and else should be on the same line as '{' or '}' >>>  > - long lines should be wrapped >>>  > - in the line: >>>  > +    return (((tag_access_register & 0x1fff)<<48)|(tag_access_register >> 22)); >>>  >  there should be white space between ) and << and 48. >>>  > >>> >> >> Also the ")|(" in between is crowded. >> >> Maybe the coding style does not describe this well enough. BTW Supplying indent template would be great. Please see the updated patch qemu-sparc64-tsb-asi-2.patch attached. -- Kind regards, Igor V. Kovalenko
2009-04-24qemu: introduce qemu_init_vcpu (Marcelo Tosatti)aliguori
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7242 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-24qemu: per-arch cpu_has_work (Marcelo Tosatti)aliguori
Blue Swirl: fix Sparc32 breakage Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7238 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-05Add new command line option -singlestep for tcg single stepping.aurel32
This replaces a compile time option for some targets and adds this feature to targets which did not have a compile time option. Add monitor command to enable or disable single step mode. Modify monitor command "info status" to display single step mode. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7004 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-16Delete some unused macros detected with -Wp,-Wunused-macros useblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6856 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-07The _exit syscall is used for both thread termination in NPTL applications,pbrook
and process termination in legacy applications. Try to guess which we want based on the presence of multiple threads. Also implement locking when modifying the CPU list. Signed-off-by: Paul Brook <paul@codesourcery.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6735 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-21Turn MMUs and caches off on resetblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6636 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-05targets: remove error handling from qemu_malloc() callers (Avi Kivity)aliguori
Signed-off-by: Avi Kivity <avi@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6530 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-26Log reset events (Jan Kiszka)aliguori
Original idea&code by Kevin Wolf, split-up in two patches and added more archs. This patch introduces a flag to log CPU resets. Useful for tracing unexpected resets (such as those triggered by x86 triple faults). Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6452 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-15global s/loglevel & X/qemu_loglevel_mask(X)/ (Eduardo Habkost)aliguori
These are references to 'loglevel' that aren't on a simple 'if (loglevel & X) qemu_log()' statement. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6340 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-15Convert references to logfile/loglevel to use qemu_log*() macrosaliguori
This is a large patch that changes all occurrences of logfile/loglevel global variables to use the new qemu_log*() macros. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6338 c046a42c-6fe2-441c-8c8c-71466251a162
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