aboutsummaryrefslogtreecommitdiff
path: root/target-sparc
AgeCommit message (Expand)Author
2008-09-10Convert basic 64 bit VIS ops to TCGblueswir1
2008-09-10Convert basic 32 bit VIS ops to TCGblueswir1
2008-09-10Convert basic float32 ops to TCGblueswir1
2008-09-09Implement ldxfsr/stxfsr, fix ld(x)fsr masks, convert to TCGblueswir1
2008-09-06Fix a typo in fpsub32blueswir1
2008-09-06Convert most env fields to TCG registersblueswir1
2008-09-06Silence gcc warning about constant overflowblueswir1
2008-09-03Implement no-fault loadsblueswir1
2008-09-02Fix sign extension problems with smul and umul (Vince Weaver)blueswir1
2008-09-01Fix y register loads and storesblueswir1
2008-08-30Remove memcpy32() prototype leftover from r5109blueswir1
2008-08-29Fix FCC handling for Sparc64 target, initial patch by Vince Weaverblueswir1
2008-08-29Fix Sparc64 boot on i386 host:blueswir1
2008-08-25Fix udiv and sdiv on Sparc64 (Vince Weaver)blueswir1
2008-08-21Fix wrwim masking (Luis Pureza)blueswir1
2008-08-21Use initial CPU definition structure for some CPU fields instead of copyingblueswir1
2008-08-17Correct 32bit carry flag for add instruction (Igor Kovalenko)blueswir1
2008-08-06Fix faligndata (Vince Weaver)blueswir1
2008-08-06Fix I/D MMU tag readsblueswir1
2008-08-06Fix Sparc64 shiftsblueswir1
2008-08-06Fix offset handling for ASI loads and stores (Vince Weaver)blueswir1
2008-08-01Handle wrapped registers correctly when savingblueswir1
2008-07-29Fix cmp/subcc/addcc op bugs reported by Vince Weaverblueswir1
2008-07-25Make MAXTL dynamic, bounds check tl when indexingblueswir1
2008-07-24Sparc32: save/load all MMU registers, Sparc64: add CPU save/loadblueswir1
2008-07-22Add T1 and T2 CPUs, add a Sun4v machineblueswir1
2008-07-21Use MMU globals for some MMU trapsblueswir1
2008-07-21Fix reset vectorblueswir1
2008-07-20Print default and available CPU features separatelyblueswir1
2008-07-20Make UA200x features selectable, add MMU typesblueswir1
2008-07-19Remove unused variableblueswir1
2008-07-19Implement nucleus quad lddablueswir1
2008-07-19Update TLB miss addressesblueswir1
2008-07-18Small cleanup of gen_intermediate_code(_internal), by Laurent Desnogues.ths
2008-07-18wrhpr hstick_cmpr is a store, not a loadblueswir1
2008-07-17Fix saving and loading of trap stateblueswir1
2008-07-17Support for address maskingblueswir1
2008-07-16Fix MMU registers, add more E-cache ASIsblueswir1
2008-07-16Fix MMU miss trapsblueswir1
2008-07-16Flushw can generate exceptions, so save PC & NPCblueswir1
2008-07-15Really fix casblueswir1
2008-07-08Implement some Ultrasparc cache ASIs used by SILOblueswir1
2008-07-01Move interrupt_request and user_mode_only to common cpu state.pbrook
2008-06-30Move CPU save/load registration to common code.pbrook
2008-06-29Add instruction counter.pbrook
2008-06-26Fix bogus format, reading uninitialised memory (original patch by Julian Seward)blueswir1
2008-06-24Fix Sparc mmu bug seen with NetBSD, based on patch by Cliff Wrightblueswir1
2008-06-23Fix compiler warning (Jan Kiszka)blueswir1
2008-06-22Eliminate cpu_T[0]blueswir1
2008-06-22Eliminate cpu_T[1]blueswir1