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path: root/target-sparc/translate.c
AgeCommit message (Expand)Author
2009-08-04Sparc64: replace tsptr with helper routineIgor Kovalenko
2009-07-31sparc64 flush pending conditional evaluations before exposing cpu stateIgor Kovalenko
2009-07-16Update to a hopefully more future proof FSF addressBlue Swirl
2009-06-06Use correct type for SPARC cpu_cc_opPaul Brook
2009-05-10Convert mulsccBlue Swirl
2009-05-10Convert udiv/sdivBlue Swirl
2009-05-10Convert tagged opsBlue Swirl
2009-05-10Convert subxBlue Swirl
2009-05-10Convert subBlue Swirl
2009-05-10Convert logical operations and umul/smulBlue Swirl
2009-05-10Convert addxBlue Swirl
2009-05-10Convert addBlue Swirl
2009-05-10Use dynamical computation for condition codesBlue Swirl
2009-05-03Optimize cmp x, 0 caseBlue Swirl
2009-05-03ReindentBlue Swirl
2009-05-02Improve instruction name comments for easier searchingBlue Swirl
2009-05-02Optimize operations with immediate parametersBlue Swirl
2009-05-02Fix Sparc64 sign extension problemsBlue Swirl
2009-04-05Add new command line option -singlestep for tcg single stepping.aurel32
2009-03-16Delete some unused macros detected with -Wp,-Wunused-macros useblueswir1
2009-01-15global s/loglevel & X/qemu_loglevel_mask(X)/ (Eduardo Habkost)aliguori
2009-01-15Convert references to logfile/loglevel to use qemu_log*() macrosaliguori
2009-01-04Update FSF address in GPL/LGPL boilerplateaurel32
2008-11-25Use sys-queue.h for break/watchpoint managment (Jan Kiszka)aliguori
2008-11-18Refactor and enhance break/watchpoint API (Jan Kiszka)aliguori
2008-11-17TCG variable type checking.pbrook
2008-11-09Use TCG not opblueswir1
2008-11-09Use andc, orc, nor and nandblueswir1
2008-11-01Fix TCGv size mismatchesblueswir1
2008-09-26Implement UA2005 hypervisor trapsblueswir1
2008-09-22Add software and timer interrupt supportblueswir1
2008-09-21Use the new concat_tl_i64 op for std and stdablueswir1
2008-09-21Use the new concat_i32_i64 op for std and stdablueswir1
2008-09-13Fix mulscc with high bits set in either src1 or src2blueswir1
2008-09-11Write zeros to high bits of y, based on patch by Vince Weaverblueswir1
2008-09-10Convert rest of ops using float32 to TCG, remove FT0 and FT1blueswir1
2008-09-10Partially convert float128 conversion ops to TCGblueswir1
2008-09-10Convert basic 64 bit VIS ops to TCGblueswir1
2008-09-10Convert basic 32 bit VIS ops to TCGblueswir1
2008-09-10Convert basic float32 ops to TCGblueswir1
2008-09-09Implement ldxfsr/stxfsr, fix ld(x)fsr masks, convert to TCGblueswir1
2008-09-06Fix a typo in fpsub32blueswir1
2008-09-06Convert most env fields to TCG registersblueswir1
2008-09-06Silence gcc warning about constant overflowblueswir1
2008-09-02Fix sign extension problems with smul and umul (Vince Weaver)blueswir1
2008-09-01Fix y register loads and storesblueswir1
2008-08-29Fix FCC handling for Sparc64 target, initial patch by Vince Weaverblueswir1
2008-08-21Fix wrwim masking (Luis Pureza)blueswir1
2008-08-21Use initial CPU definition structure for some CPU fields instead of copyingblueswir1
2008-08-17Correct 32bit carry flag for add instruction (Igor Kovalenko)blueswir1
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