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Scripted conversion:
sed -i "s/CPUState/CPUSPARCState/g" target-sparc/*.[hc]
sed -i "s/#define CPUSPARCState/#define CPUState/" target-sparc/cpu.h
Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Anthony Liguori <aliguori@us.ibm.com>
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This allows a more efficient representation for 64-bit hosts.
It should be about the same for 32-bit hosts, as we can still
access the individual pieces of the double.
Signed-off-by: Richard Henderson <rth@twiddle.net>
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Most exec-all.h include directives are now useless, remove them.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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Add dummy registers for SuperSPARC MXCC MMU counter breakpoints, save
and load all MXCC registers.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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Recalculate Sparc64 CPU flags on interrupts, otherwise some earlier
flags could be stored to pstate.
Refactor PSR/CCR/CWP handling: concentrate the actual
functions to op_helper.c.
Thanks to Igor Kovalenko for reporting.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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sparc64 timer has tick counter which can be set and read,
and tick compare value used as deadline to fire timer interrupt.
The timer is not used as periodic timer, instead deadline
is set each time new timer interrupt is needed.
v3 -> v4:
- coding style
v2 -> v3:
- added missing timer debug output macro
- CPUTimer struct and typedef moved to cpu.h
- change CPU_SAVE_VERSION to 6, older save formats not supported
v1 -> v2:
- new conversion helpers cpu_to_timer_ticks and timer_to_cpu_ticks
- save offset from clock source to implement cpu_tick_set_count
- renamed struct sun4u_timer to CPUTimer
- load and save cpu timers
v0 -> v1:
- coding style
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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tl and tsptr of members sparc64 cpu state must be changed
simultaneously to keep trap state window in sync with current
trap level. Currently translation of store to tl does not change
tsptr, which leads to corrupt trap state on corresponding
trap level.
This patch removes tsptr from sparc64 cpu state and replaces
all uses with call to helper routine.
Changes v0->v1:
- reimplemented helper routine with tcg generator
- on cpu reset trap type and pstate are populated with power-on reset
values, including tl=maxtl
Signed-off-by: igor.v.kovalenko@gmail.com
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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- add names to mmu registers, this helps understanding the code which
uses/modifies them.
- fold i/d mmu tlb entries tag and tte arrays into arrays of tlb entries
- extract demap_tlb routine (code duplication)
- extract replace_tlb routine (code duplication)
- flush qemu tlb translations when replacing sparc64 mmu tlb entries
I have no test case which demands flushing qemu translations,
and this patch should have no other visible changes to runtime.
Signed-off-by: igor.v.kovalenko@gmail.com
--
Kind regards,
Igor V. Kovalenko
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This cleans up quite a lot of #ifdefs, extern variables, and other ugliness.
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6000 c046a42c-6fe2-441c-8c8c-71466251a162
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5329 c046a42c-6fe2-441c-8c8c-71466251a162
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Fix typo
Save and load interrupt_index and pil_in
Original patch by Luis Pureza
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4980 c046a42c-6fe2-441c-8c8c-71466251a162
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4942 c046a42c-6fe2-441c-8c8c-71466251a162
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4938 c046a42c-6fe2-441c-8c8c-71466251a162
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4923 c046a42c-6fe2-441c-8c8c-71466251a162
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4690 c046a42c-6fe2-441c-8c8c-71466251a162
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(Glauber Costa)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4327 c046a42c-6fe2-441c-8c8c-71466251a162
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