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path: root/target-sparc/helper.h
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2010-05-20target-sparc: Inline some generation of carry for ADDX/SUBX.Richard Henderson
Computing carry is trivial for some inputs. By avoiding an external function call, we generate near-optimal code for the common cases of add+addx (double-word arithmetic) and cmp+addx (a setcc pattern). Signed-off-by: Richard Henderson <rth@twiddle.net> Acked-by: Artyom Tarasenko <atar4qemu@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-05-19target-sparc: Fix compilation with --enable-debug.Richard Henderson
Return a target_ulong from compute_C_icc to match the width of the users. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-01-08sparc64: use helper_wrpil to check pending irq on writeIgor V. Kovalenko
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-05-10Use dynamical computation for condition codesBlue Swirl
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2008-11-17TCG variable type checking.pbrook
Signed-off-by: Paul Brook <paul@codesourcery.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-26Implement UA2005 hypervisor trapsblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5327 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-22Add software and timer interrupt supportblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5299 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-21Use the new concat_i32_i64 op for std and stdablueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5281 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-10Convert rest of ops using float32 to TCG, remove FT0 and FT1blueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5193 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-10Partially convert float128 conversion ops to TCGblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5192 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-10Convert basic 64 bit VIS ops to TCGblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5191 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-10Convert basic 32 bit VIS ops to TCGblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5190 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-10Convert basic float32 ops to TCGblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5189 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-09Implement ldxfsr/stxfsr, fix ld(x)fsr masks, convert to TCGblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5185 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-29Fix Sparc64 boot on i386 host:blueswir1
- move do_interrupt() back to op_helper.c - move non-helper prototypes from helper.h to exec.h - move some prototypes from cpu.h to exec.h - do not export either set_cwp() or cpu_set_cwp() from op_helper.c, but instead provide inline functions git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5109 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-19Implement nucleus quad lddablueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4902 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-27Move non-op functions from op_helper.c to helper.c and vice versa.blueswir1
Rearrange interrupt handling to match other targets. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4590 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-22Register op helpersblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4534 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-12Move prototype back to avoid a compiler warningblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4443 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-10Fix compiler warningsblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4404 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-09CPU feature selection supportblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4399 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-04Complete the TCG conversionblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4323 c046a42c-6fe2-441c-8c8c-71466251a162
2008-03-21 Convert align checks to TCGblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4097 c046a42c-6fe2-441c-8c8c-71466251a162
2008-03-21 Convert save, restore, saved, restored, and flushw to TCGblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4092 c046a42c-6fe2-441c-8c8c-71466251a162
2008-03-21 Convert other float and VIS ops to TCGblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4091 c046a42c-6fe2-441c-8c8c-71466251a162
2008-03-18 Convert udiv and sdiv ops to TCGblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4088 c046a42c-6fe2-441c-8c8c-71466251a162
2008-03-18 Convert CCR and CWP ops to TCGblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4086 c046a42c-6fe2-441c-8c8c-71466251a162
2008-03-18 Convert array8/16/32 and alignaddr to TCGblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4085 c046a42c-6fe2-441c-8c8c-71466251a162
2008-03-15 Convert ldfsr and stfsr to TCGblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4067 c046a42c-6fe2-441c-8c8c-71466251a162
2008-03-06 Convert exception ops to TCGblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4022 c046a42c-6fe2-441c-8c8c-71466251a162
2008-03-04 Convert float helpers to TCG, fix fabsq in the processblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4014 c046a42c-6fe2-441c-8c8c-71466251a162
2008-03-02 Convert tick operations to TCGblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4011 c046a42c-6fe2-441c-8c8c-71466251a162
2008-02-24 Modify Sparc32/64 to use TCGblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3989 c046a42c-6fe2-441c-8c8c-71466251a162
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