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2010-05-12target-sparc: Fix wrong printf argumentStefan Weil
cpu_get_ccr() returns a target_ulong, so a type cast is needed to avoid wrong output on big endian hosts. We could also use TARGET_FMT_lx, but that would print 8 instead of 2 digits. Cc: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-05-09sparc: Fix lazy flag calculation on interrupts, refactorBlue Swirl
Recalculate Sparc64 CPU flags on interrupts, otherwise some earlier flags could be stored to pstate. Refactor PSR/CCR/CWP handling: concentrate the actual functions to op_helper.c. Thanks to Igor Kovalenko for reporting. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-05-07sparc64: fix build with older gccsBlue Swirl
Fix errors missed in 2065061ede22d401aae2ce995c3af54db9d28639: CC sparc64-softmmu/helper.o cc1: warnings being treated as errors /src/qemu/target-sparc/helper.c: In function 'get_physical_address': /src/qemu/target-sparc/helper.c:426: warning: 'context' may be used uninitialized in this function /src/qemu/target-sparc/helper.c:426: note: 'context' was declared here Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-05-06sparc64: handle asi referencing nucleus and secondary MMU contextsIgor V. Kovalenko
- increase max supported MMU modes to 6 - handle nucleus context asi - handle secondary context asi - handle non-faulting loads from secondary context Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-05-06sparc64: implement global translation table entries v1Igor V. Kovalenko
- match global tte against any context - show global tte in MMU dump v0->v1: added default case to switch statement in demap_tlb - should fix gcc warning about uninitialized context variable Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-03-17Large page TLB flushPaul Brook
QEMU uses a fixed page size for the CPU TLB. If the guest uses large pages then we effectively split these into multiple smaller pages, and populate the corresponding TLB entries on demand. When the guest invalidates the TLB by virtual address we must invalidate all entries covered by the large page. However the address used to invalidate the entry may not be present in the QEMU TLB, so we do not know which regions to clear. Implementing a full vaiable size TLB is hard and slow, so just keep a simple address/mask pair to record which addresses may have been mapped by large pages. If the guest invalidates this region then flush the whole TLB. Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-03-12Remove cpu_get_phys_page_debug from userspace emulationPaul Brook
cpu_get_phys_page_debug makes no sense for userspace emulation, so remove it. Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-01-31sparc32 don't mark page dirty when failingArtyom Tarasenko
if the access check fails, the page can not be modified and shouldn't be marked dirty. The patch fixes the "hsfs_putpage: dirty HSFS page" error in Solaris guests. Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-01-17Sparc: improve CPU register dumpBlue Swirl
Common: * Remove unnecessary 0x prefix * Print %y * Fix NZVC flag print order to match CPU bit order Sparc64 specific: * Print registers without line wrapping * Print %f40-%f63 * Pretty print CCR flags * Print %fsr and %fprs in full precision * More consistent formatting Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-01-13Sparc32: remove unused variable, spotted by clangBlue Swirl
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2010-01-08sparc64: add PIL to cpu state dumpIgor V. Kovalenko
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-12-05Sparc64: handle MMU global bit and nucleus contextBlue Swirl
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-12-04Sparc64: fix compilation with DEBUG_MMUBlue Swirl
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-11-07user: move CPU reset call to main.c for x86/PPC/SparcBlue Swirl
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-11-07sparc32 (mostly): remove unneeded calls to device resetBlue Swirl
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-10-01Revert "Get rid of _t suffix"Anthony Liguori
In the very least, a change like this requires discussion on the list. The naming convention is goofy and it causes a massive merge problem. Something like this _must_ be presented on the list first so people can provide input and cope with it. This reverts commit 99a0949b720a0936da2052cb9a46db04ffc6db29. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-01Get rid of _t suffixmalc
Some not so obvious bits, slirp and Xen were left alone for the time being. Signed-off-by: malc <av1474@comtv.ru>
2009-08-18Sparc32/64: Fix user emulator breakageBlue Swirl
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-08-04Sparc64: replace tsptr with helper routineIgor Kovalenko
tl and tsptr of members sparc64 cpu state must be changed simultaneously to keep trap state window in sync with current trap level. Currently translation of store to tl does not change tsptr, which leads to corrupt trap state on corresponding trap level. This patch removes tsptr from sparc64 cpu state and replaces all uses with call to helper routine. Changes v0->v1: - reimplemented helper routine with tcg generator - on cpu reset trap type and pstate are populated with power-on reset values, including tl=maxtl Signed-off-by: igor.v.kovalenko@gmail.com Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-07-27sparc64 really implement itlb/dtlb automatic replacement writesIgor Kovalenko
- implement "used" bit in tlb translation entry - mark tlb entry used if qemu code/data translation succeeds - fold i/d mmu replacement writes code into replace_tlb_1bit_lru which adds 1bit lru replacement algorithm; previously code tried to replace first unlocked entry only - extract more bitmasks to named macros - add "immu" or "dmmu" type name to debugging output where appropriate Signed-off-by: igor.v.kovalenko@gmail.com -- Kind regards, Igor V. Kovalenko
2009-07-27sparc64 name mmu registers and general cleanupIgor Kovalenko
- add names to mmu registers, this helps understanding the code which uses/modifies them. - fold i/d mmu tlb entries tag and tte arrays into arrays of tlb entries - extract demap_tlb routine (code duplication) - extract replace_tlb routine (code duplication) - flush qemu tlb translations when replacing sparc64 mmu tlb entries I have no test case which demands flushing qemu translations, and this patch should have no other visible changes to runtime. Signed-off-by: igor.v.kovalenko@gmail.com -- Kind regards, Igor V. Kovalenko
2009-07-20Fix most warnings (errors with -Werror) when debugging is enabledBlue Swirl
I used the following command to enable debugging: perl -p -i -e 's/^\/\/#define DEBUG/#define DEBUG/g' * */* */*/* Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-07-16Update to a hopefully more future proof FSF addressBlue Swirl
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-07-12sparc64: trap handling correctionsIgor Kovalenko
On Sun, Jul 12, 2009 at 12:09 PM, Blue Swirl<blauwirbel@gmail.com> wrote: > On 7/12/09, Igor Kovalenko <igor.v.kovalenko@gmail.com> wrote: >> Good trap handling is required to process interrupts. >>  This patch fixes the following: >> >>  - sparc64 has no wim register >>  - sparc64 has no psret register, use IE bit of pstate >>   extract IE checking code to cpu_interrupts_enabled >>  - alternate globals are not available if cpu has GL feature >>   in this case bit AG of pstate is constant zero >>  - write to pstate must actually write pstate >>   even if cpu has GL feature >> >>  Also timer interrupt is handled using do_interrupt. > > A bit too much for one patch. Please also remove the code instead of > commenting out. I now excluded timer interrupt related part. To my mind other changes are essentially tied together. > PUT_PSR for Sparc64 needs CC_OP = CC_OP_FLAGS; like Sparc32. Fixed, please find attached the updated version. -- Kind regards, Igor V. Kovalenko
2009-07-12sparc64: unify mmu tag matching codeIgor Kovalenko
This patch extracts common part of sparc64 tag matching code used by IMMU and DMMU lookups. Signed-off-by: igor.v.kovalenko@gmail.com -- Kind regards, Igor V. Kovalenko
2009-07-12sparc64: mmu bypass mode correctionIgor Kovalenko
This Implement physical address truncation in mmu bypass mode. IMMU bypass is also active when cpu enters RED_STATE Signed-off-by: igor.v.kovalenko@gmail.com -- Kind regards, Igor V. Kovalenko
2009-05-13Include assert.h from qemu-common.hPaul Brook
Include assert.h from qemu-common.h and remove other direct uses. cpu-all.h still need to include it because of the dyngen-exec.h hacks Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-05-10Use dynamical computation for condition codesBlue Swirl
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-05-02Clarify: dmmuregs[1] is not a typoBlue Swirl
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-04-28sparc64 fix context value for ITLB faultIgor Kovalenko
Revert previous change to get_physical_address_code: I/D MMU context register is shared, so using dmmuregs[1] is correct Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
2009-04-27sparc64 fix TLB match codeIgor Kovalenko
TLB match code must respect page size, otherwise 4M page mappings may be not found. Also correct a typo in get_physical_address_code which should use IMMU registers. Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com> -- Kind regards, Igor V. Kovalenko
2009-04-24qemu: introduce qemu_init_vcpu (Marcelo Tosatti)aliguori
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7242 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-16Delete some unused macros detected with -Wp,-Wunused-macros useblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6856 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-21Turn MMUs and caches off on resetblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6636 c046a42c-6fe2-441c-8c8c-71466251a162
2009-02-05targets: remove error handling from qemu_malloc() callers (Avi Kivity)aliguori
Signed-off-by: Avi Kivity <avi@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6530 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-26Log reset events (Jan Kiszka)aliguori
Original idea&code by Kevin Wolf, split-up in two patches and added more archs. This patch introduces a flag to log CPU resets. Useful for tracing unexpected resets (such as those triggered by x86 triple faults). Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6452 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-14Get rid of user_mode_onlyaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6305 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-12Fix TLB access (Jakub Jermar)blueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6274 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-04Update FSF address in GPL/LGPL boilerplateaurel32
The attached patch updates the FSF address in the GPL/LGPL boilerplate in most GPL/LGPLed files, and also in COPYING.LIB. Signed-off-by: Stuart Brady <stuart.brady@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6162 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-23Better SuperSPARC emulation (Robert Reif)blueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6123 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-22Use the ARRAY_SIZE() macro where appropriate.malc
Change from v1: Avoid changing the existing coding style in certain files. Signed-off-by: Stuart Brady <stuart.brady@gmail.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6120 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-07Add static (spotted by sparse)blueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5439 c046a42c-6fe2-441c-8c8c-71466251a162
2008-10-03Rearrange tick functionsblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5408 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-26Add a generic Niagara machineblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5329 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-26Move also DEBUG_PCALL (see r5085)blueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5326 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-09Implement ldxfsr/stxfsr, fix ld(x)fsr masks, convert to TCGblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5185 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-29Fix Sparc64 boot on i386 host:blueswir1
- move do_interrupt() back to op_helper.c - move non-helper prototypes from helper.h to exec.h - move some prototypes from cpu.h to exec.h - do not export either set_cwp() or cpu_set_cwp() from op_helper.c, but instead provide inline functions git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5109 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-21Use initial CPU definition structure for some CPU fields instead of copyingblueswir1
them around, based on patch by Luis Pureza. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5042 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-25Make MAXTL dynamic, bounds check tl when indexingblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4942 c046a42c-6fe2-441c-8c8c-71466251a162
2008-07-22Add T1 and T2 CPUs, add a Sun4v machineblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4923 c046a42c-6fe2-441c-8c8c-71466251a162
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