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path: root/target-sh4/op_helper.c
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2011-10-01softmmu_header: pass CPUState to tlb_fillBlue Swirl
Pass CPUState pointer to tlb_fill() instead of architecture local cpu_single_env hacks. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-08-07Remove unused is_softmmu parameter from cpu_handle_mmu_faultBlue Swirl
Parameter is_softmmu (and its evil mutant twin brother is_softmuu) is not used in cpu_*_handle_mmu_fault() functions, remove them and adjust callers. Acked-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-07-30exec.h cleanupBlue Swirl
Move softmmu_exec.h include directives from target-*/exec.h to target-*/op_helper.c. Move also various other stuff only used in op_helper.c there. Define global env in dyngen-exec.h. For i386, move wrappers for segment and FPU helpers from user-exec.c to op_helper.c. Implement raise_exception_err_env() to handle dynamic CPUState. Move the function declarations to cpu.h since they can be used outside of op_helper.c context. LM32, s390x, UniCore32: remove unused cpu_halted(), regs_to_env() and env_to_regs(). ARM: make raise_exception() static. Convert #include "exec.h" to #include "cpu.h" #include "dyngen-exec.h" and remove now unused target-*/exec.h. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-06-26cpu_loop_exit: avoid using AREG0Blue Swirl
Make cpu_loop_exit() take a parameter for CPUState instead of relying on global env. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-04-20Remove unused function parameter from cpu_restore_stateStefan Weil
The previous patch removed the need for parameter puc. Is is now unused, so remove it. Cc: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stefan Weil <weil@mail.berlios.de>
2011-04-12target-sh4: get rid of CPU_{Float,Double}UAurelien Jarno
SH4 is always using softfloat, so it's possible to have helpers directly taking float32 or float64 value. This allow to get rid of conversions through CPU_{Float,Double}U. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-03target-sh4: move intr_at_halt out of cpu_halted()Aurelien Jarno
All targets except SH4 have the same cpu_halted() routine, and it has only one caller. It is therefore a good candidate for inlining. The difference is the handling of the intr_at_halt, which is necessary to ignore SR.BL when sleeping. Move intr_at_halt handling out of it, by setting this variable while executing the sleep instruction, and clearing it when the CPU has been woken-up by an interrupt, whatever the state of SR.BL. Also rename this variable in_sleep. Cc: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-16target-sh4: implement negc using TCGAurelien Jarno
Using setcond it's now possible to generate a relatively short negc instruction in TCG. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-sh4: optimize exceptionsAurelien Jarno
As exception is not the normal path, don't bother saving PC, before raising one, instead rely on code retranslation to get the CPU state. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-sh4: add ftrv instructionAurelien Jarno
Add the ftrv XMTRX,FVn instruction, which computes the 4-row x 4-column matrix XMTRX by the 4-dimensional vector FVn. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-sh4: add fipr instructionAurelien Jarno
Add the fipr FVm,FVn instruction, which computes the inner products of a 4-dimensional single precision floating-point vector. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-sh4: implement FPU exceptionsAurelien Jarno
FPU exception support where not implemented on SH4. Implement them by clearing the softfloat exceptions flags before an FP instruction (the SH4 FPU also clear them before an instruction), and calling a function to update the FPSCR register after an FP instruction. This function update the corresponding FPSCR bits (both flags and cumulative flags) and trigger exception if enabled. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-sh4: implement flush-to-zeroAurelien Jarno
When the FPSCR.DN bit is set, the SH4 FPU treat denormalized numbers as zero. Enable the corresponding softfloat option when this bit is set. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-01-14target-sh4: define FPSCR constantsAurelien Jarno
Define FPSCR constants for all field and use them instead of hardcoded values. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2010-03-18Replace assert(0) with abort() or cpu_abort()Blue Swirl
When building with -DNDEBUG, assert(0) will not stop execution so it must not be used for abnormal termination. Use cpu_abort() when in CPU context, abort() otherwise. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-09-21Fix Sparse warnings about using plain integer as NULL pointerBlue Swirl
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-07-16Update to a hopefully more future proof FSF addressBlue Swirl
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-04-01SH: Improve movca.l/ocbi emulation.edgar_igl
Author: Vladimir Prus <vladimir@codesourcery.com> Fix movcal.l/ocbi emulation. * target-sh4/cpu.h (memory_content): New. (CPUSH4State): New fields movcal_backup and movcal_backup_tail. * target-sh4/helper.h (helper_movcal) (helper_discard_movcal_backup, helper_ocbi): New. * target-sh4/op_helper.c (helper_movcal) (helper_discard_movcal_backup, helper_ocbi): New. * target-sh4/translate.c (DisasContext): New field has_movcal. (sh4_defs): Update CVS for SH7785. (cpu_sh4_init): Initialize env->movcal_backup_tail. (_decode_opc): Discard movca.l-backup. Make use of helper_movcal and helper_ocbi. (gen_intermediate_code_internal): Initialize has_movcal to 1. Thanks to Shin-ichiro KAWASAKI and Paul Mundt for valuable feedback. Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6966 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-14sh4: Add FMAC instruction supportaurel32
Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Lionel Landwerlin <lionel.landwerlin@openwide.fr> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6309 c046a42c-6fe2-441c-8c8c-71466251a162
2009-01-04Update FSF address in GPL/LGPL boilerplateaurel32
The attached patch updates the FSF address in the GPL/LGPL boilerplate in most GPL/LGPLed files, and also in COPYING.LIB. Signed-off-by: Stuart Brady <stuart.brady@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6162 c046a42c-6fe2-441c-8c8c-71466251a162
2008-12-07SH4: Implement FD bitaurel32
SH4 manual say that if a floating point instruction is executed while FD bit in the status register is 1, an exception should be raised. QEMU presently does not do that, so the kernel does not initialize FP state for any thread, nor does it save/restore FP state. The most apparent consequence is that while recent gcc/libc expect double-precision mode to be set by kernel, they run in single-precision mode, and all FP code produces wrong values. This patch fixes this. It also fixes a couple of places where PC was not updated before handling an exception, although both those places deal with invalid instruction and don't lead to any user-visible bugs. (Vladimir Prus) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5937 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-19target-sh4: use CPU_Float/CPU_Double instead of ugly castsaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5757 c046a42c-6fe2-441c-8c8c-71466251a162
2008-11-17TCG variable type checking.pbrook
Signed-off-by: Paul Brook <paul@codesourcery.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-15SH4: sleep instruction bug fixaurel32
fix a bug on 'sleep' instruction, which have caused halt of idle task. As i386 'hlt' instruction does, it should save PC before sleep. (Shin-ichiro KAWASAKI) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5220 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-01SH4: final conversion to TCGaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5125 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-01SH4: convert floating-point ops to TCGaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5124 c046a42c-6fe2-441c-8c8c-71466251a162
2008-09-01SH4: Convert remaining non-fp ops to TCGaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5120 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-30SH4: convert control/status register load/store to TCGaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5118 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-30SH4: convert some more arithmetics ops to TCGaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5116 c046a42c-6fe2-441c-8c8c-71466251a162
2008-08-29SH4: convert a few helpers to TCGaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5112 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-25Fix off-by-one unwinding error.pbrook
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4570 c046a42c-6fe2-441c-8c8c-71466251a162
2008-05-09SH4 MMU improvementsaurel32
(Shin-ichiro KAWASAKI) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4396 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-29Adjust s390 addresses (the MSB is defined as "to be ignored").ths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3486 c046a42c-6fe2-441c-8c8c-71466251a162
2007-10-14Replace is_user variable with mmu_idx in softmmu core,j_mayer
allowing support of more than 2 mmu access modes. Add backward compatibility is_user variable in targets code when needed. Implement per target cpu_mmu_index function, avoiding duplicated code and #ifdef TARGET_xxx in softmmu core functions. Implement per target mmu modes definitions. As an example, add PowerPC hypervisor mode definition and Alpha executive and kernel modes definitions. Optimize PowerPC case, precomputing mmu_idx when MSR register changes and using the same definition in code translation code. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3384 c046a42c-6fe2-441c-8c8c-71466251a162
2007-09-16find -type f | xargs sed -i 's/[\t ]$//g' # on most filesths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3173 c046a42c-6fe2-441c-8c8c-71466251a162
2007-06-03Clean up of some target specifics in exec.c/cpu-exec.c.ths
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2936 c046a42c-6fe2-441c-8c8c-71466251a162
2006-06-17Remove debug output.pbrook
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1990 c046a42c-6fe2-441c-8c8c-71466251a162
2006-04-27sh4 target (Samuel Tardieu)bellard
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1861 c046a42c-6fe2-441c-8c8c-71466251a162
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