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2016-09-07ppc: Don't update NIP in lswi/lswx/stswi/stswxBenjamin Herrenschmidt
Instead, pass GETPC() result to the corresponding helpers. This requires a bit of fiddling to get the PC (hopefully) right in the case where we generate a program check, though the hacks there are temporary, a subsequent patch will clean this all up by always having the nip already set to the right instruction when taking the fault. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [dwg: Fix trivial checkpatch warning] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: FP exceptions are always preciseBenjamin Herrenschmidt
We don't implement imprecise FP exceptions and using store_current which sets SRR1 to the *previous* instruction never makes sense for these. So let's be truthful and make them precise, which is allowed by the architecture. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Don't update the NIP in floating point generated codeBenjamin Herrenschmidt
This is no longer necessary as the helpers will properly retrieve the return address. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Make float_check_status() pass the return addressBenjamin Herrenschmidt
Instead of relying on NIP having been updated already. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [dwg: Fold in fix to mark function always_inline] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Make float_invalid_op_excp() pass the return addressBenjamin Herrenschmidt
Instead of relying on NIP having been updated already Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Rename fload_invalid_op_excp to float_invalid_op_excpBenjamin Herrenschmidt
No other change Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Move VSX ops out of translate.cBenjamin Herrenschmidt
Makes things a bit more manageable Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Move VMX ops out of translate.cBenjamin Herrenschmidt
Makes things a bit more manageable Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Move DFP ops out of translate.cBenjamin Herrenschmidt
Makes things a bit more manageable Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Move embedded spe ops out of translate.cBenjamin Herrenschmidt
Makes things a bit more manageable Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Move classic fp ops out of translate.cBenjamin Herrenschmidt
Makes things a bit more manageable Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Provide basic raise_exception_* functionsBenjamin Herrenschmidt
Instead of using the same helpers called from translate.c, let's have a bunch of functions that take the various argument combinations, especially the retaddr which will be needed in subsequent patches, and leave the helpers to be just that, helpers for translate.c We don't yet convert all users, we'll go through them in subsequent patches. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> -- v2. Fix raise_exception_ra() to properly pass raddr Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: introduce opc4 for Expanded OpcodeNikunj A Dadhania
ISA 3.0 has introduced EO - Expanded Opcode. Introduce third level indirect opcode table and corresponding parsing routines. EO (11:12) Expanded opcode field Formats: XX1 EO (11:15) Expanded opcode field Formats: VX, X, XX2 Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> [dwg: Trivial checkpatch fixup] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: add maddhd and maddhdu instructionNikunj A Dadhania
maddhd: Multiply-Add High Doubleword maddhdu: Multiply-Add High Doubleword Unsigned Above two instruction are dual form and differ by 1 bit (31st bit) Multiplies two 64-bit registers (RA * RB), adds third register(RC) to the result(quadword) and returns the higher dword in the target register(RT). Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: add maddld instructionNikunj A Dadhania
maddld: Multiply-Add Low Doubleword Multiplies two 64-bit registers (RA * RB), adds third register(RC) to the result(quadword) and returns the lower dword in the target register(RT). Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: add setb instructionVivek Andrew Sha
The CR number is provided in the opcode as - BFA (11:13) Returns: -1 if bit 0 of CR field is set 1 if bit 1 of CR field is set 0 otherwise. Signed-off-by: Vivek Andrew Sha <vivekandrewsha@gmail.com> [ reworded commit, used 32bit ops as crf is 32bits ] Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: add cmpeqb instructionNikunj A Dadhania
Search a byte in the stream of 8bytes provided in the register Suggested-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: add cnttzw[.] instructionNikunj A Dadhania
Add ISA3.0: Count trailing zeros word instruction. Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: add cnttzd[.] instructionSandipan Das
Add ISA3.0 Count trailing zeros double word Signed-off-by: Sandipan Das <sandipandas1990@gmail.com> [ added ISA300 flag ] Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: add modulo dword operationsNikunj A Dadhania
Adding following instructions for ISA3.0 support modud: Modulo Unsigned Dword modsd: Modulo Signed Dword Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: add modulo word operationsNikunj A Dadhania
Adding following instructions: moduw: Modulo Unsigned Word modsw: Modulo Signed Word Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: add cmprb instructionNikunj A Dadhania
ISA 3.0 Compare Ranged Byte instruction useful for isupper/islower/isaplha kind of operation. Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: adding addpcis instructionNikunj A Dadhania
ISA 3.0 instruction for adding immediate value shifted with next instruction address and return the result in the target register. Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: Introduce POWER ISA 3.0 flagNikunj A Dadhania
This flag will be used for POWER9 instructions. Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: Introduce Power9 familyAneesh Kumar K.V
The patch adds CPU PVR definition for POWER9 and enables QEMU to launch guests/linux-user in TCG mode. Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> [ Added POWER9 alias, POWER9 SPAPR core and dropped MMU defines ] Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> [dwg: Dropped sPAPR core type again for now] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-08-12trace-events: fix first line comment in trace-eventsLaurent Vivier
Documentation is docs/tracing.txt instead of docs/trace-events.txt. find . -name trace-events -exec \ sed -i "s?See docs/trace-events.txt for syntax documentation.?See docs/tracing.txt for syntax documentation.?" \ {} \; Signed-off-by: Laurent Vivier <lvivier@redhat.com> Message-id: 1470669081-17860-1-git-send-email-lvivier@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2016-08-10ppc/kvm: Register also a generic spapr CPU core family typeThomas Huth
There is a regression with the "-cpu" parameter introduced by the spapr CPU hotplug code: We used to allow to specify a "CPU family" name with the "-cpu" parameter when running on KVM so that the user does not need to know the gory details of the exact CPU version of the host CPU. For example, it was possible to use "-cpu POWER8" on a POWER8E host CPU. This behavior does not work anymore with the new hot-pluggable spapr-cpu-core types. Since libvirt already heavily depends on the old behavior, this is quite a severe regression in the QEMU parameter interface. Let's fix it by supporting a CPU family type for the spapr-cpu-core on KVM, too. Buglink: https://bugzilla.redhat.com/show_bug.cgi?id=1363812 Signed-off-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-08-10ppc/kvm: Do not mess up the generic CPU family registrationThomas Huth
The code for registering the sPAPR CPU host core type has been added inbetween the generic CPU host core type and the generic CPU family type. That way the instance_init and the class_init information got lost when registering the generic CPU family type. Fix it by moving the generic family registration before the spapr cpu core registration code. Signed-off-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-08-10ppc: Introduce a function to look up CPU alias stringsThomas Huth
We will need this function to look up the aliases in the spapr-cpu-core code, too. Signed-off-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-08-10ppc64: fix compressed dump with pseries kernelLaurent Vivier
If we don't provide the page size in target-ppc:cpu_get_dump_info(), the default one (TARGET_PAGE_SIZE, 4KB) is used to create the compressed dump. It works fine with Macintosh, but not with pseries as the kernel default page size is 64KB. Without this patch, if we generate a compressed dump in the QEMU monitor: (qemu) dump-guest-memory -z qemu.dump This dump cannot be read by crash: # crash vmlinux qemu.dump ... WARNING: cannot translate vmemmap kernel virtual addresses: commands requiring page structure contents will fail ... Page_size is used to determine the dumpfile's block size. The block size needs to be at least the page size, but a multiple of page size works fine too. For PPC64, linux supports either 4KB or 64KB software page size. So we define the page_size to 64KB. Signed-off-by: Laurent Vivier <lvivier@redhat.com> Reviewed-by: Andrew Jones <drjones@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-07-29ppc: Fix fault PC reporting for lve*/stve* VMX instructionsBenjamin Herrenschmidt
We forgot to do gen_update_nip() for these like we do with other helpers. Fix this, but in a more efficient way by passing the RA to the accessors instead so the overhead is only taken on faults. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-07-25target-ppc: add PPC_MFTB flag to e500mc and e5500Michael Walle
According to the e500mc and e5500 core reference manual they have support for the mftb instruction. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-07-25ppc: Huge page detection mechanism fixes - Episode IIIThomas Huth
After already fixing two issues with the huge page detection mechanism (see commit 159d2e39a860 and 86b50f2e1bef), Greg Kurz noticed another case that caused the guest to crash where QEMU announces huge pages though they should not be available for the guest: qemu-system-ppc64 -enable-kvm ... -mem-path /dev/hugepages \ -m 1G,slots=4,maxmem=32G -object memory-backend-ram,policy=default,size=1G,id=mem-mem1 \ -device pc-dimm,id=dimm-mem1,memdev=mem-mem1 -smp 2 \ -numa node,nodeid=0 -numa node,nodeid=1 That means if there is a global mem-path option, we still have to look at the memory-backend objects that have been specified additionally and return their minimum page size if that value is smaller than the page size of the main memory. Reported-by: Greg Kurz <groug@kaod.org> Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Greg Kurz <groug@kaod.org> Tested-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-07-21kvm-irqchip: i386: add hook for add/remove virqPeter Xu
Adding two hooks to be notified when adding/removing msi routes. There are two kinds of MSI routes: - in kvm_irqchip_add_irq_route(): before assigning IRQFD. Used by vhost, vfio, etc. - in kvm_irqchip_send_msi(): when sending direct MSI message, if direct MSI not allowed, we will first create one MSI route entry in the kernel, then trigger it. This patch only hooks the first one (irqfd case). We do not need to take care for the 2nd one, since it's only used by QEMU userspace (kvm-apic) and the messages will always do in-time translation when triggered. While we need to note them down for the 1st one, so that we can notify the kernel when cache invalidation happens. Also, we do not hook IOAPIC msi routes (we have explicit notifier for IOAPIC to keep its cache updated). We only need to care about irqfd users. Signed-off-by: Peter Xu <peterx@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2016-07-18ppc: Yet another fix for the huge page support detection mechanismThomas Huth
Commit 86b50f2e1bef ("Disable huge page support if it is not available for main RAM") already made sure that huge page support is not announced to the guest if the normal RAM of non-NUMA configurations is not backed by a huge page filesystem. However, there is one more case that can go wrong: NUMA is enabled, but the RAM of the NUMA nodes are not configured with huge page support (and only the memory of a DIMM is configured with it). When QEMU is started with the following command line for example, the Linux guest currently crashes because it is trying to use huge pages on a memory region that does not support huge pages: qemu-system-ppc64 -enable-kvm ... -m 1G,slots=4,maxmem=32G -object \ memory-backend-file,policy=default,mem-path=/hugepages,size=1G,id=mem-mem1 \ -device pc-dimm,id=dimm-mem1,memdev=mem-mem1 -smp 2 \ -numa node,nodeid=0 -numa node,nodeid=1 To fix this issue, we've got to make sure to disable huge page support, too, when there is a NUMA node that is not using a memory backend with huge page support. Fixes: 86b50f2e1befc33407bdfeb6f45f7b0d2439a740 Signed-off-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-07-18target-ppc: fix left shift overflow in hpte_page_shiftPaolo Bonzini
ps->pte_enc is a 32-bit value, which is shifted left and then compared to a 64-bit value. It needs a cast before the shift. Reported by Coverity. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-07-18ppc/mmu-hash64: Remove duplicated #include statementThomas Huth
No need to include error-report.h twice here. Signed-off-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-07-18ppc: abort if compat property contains an unknown valueGreg Kurz
It is not possible to set the compat property to an unknown value with powerpc_set_compat(). Something must have gone terribly wrong in QEMU, if we detect an "Internal error" in powerpc_get_compat(). Let's abort then. This patch also drops the "max_compat ? *max_compat : -1" construct. It is useless since max_compat is dereferenced a few lines above. Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-07-18ppc: Fix support for odd MSR combinationsBenjamin Herrenschmidt
MacOS uses an architecturally illegal MSR combination that seems nonetheless supported by 32-bit processors, which is to have MSR[PR]=1 and one or more of MSR[DR/IR/EE]=0. This adds support for it. To work properly we need to also properly include support for PR=1,{I,D}R=0 to the MMU index used by the qemu TLB. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-07-12Clean up ill-advised or unusual header guardsMarkus Armbruster
Cleaned up with scripts/clean-header-guards.pl. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Richard Henderson <rth@twiddle.net>
2016-07-12target-*: Clean up cpu.h header guardsMarkus Armbruster
Most of them use guard symbols like CPU_$target_H, but we also have __MIPS_CPU_H__ and __TRICORE_CPU_H__. They all upset scripts/clean-header-guards.pl. The script dislikes CPU_$target_H because they don't match their file name (they should, to make guard collisions less likely). The others are reserved identifiers. Clean them all up: use guard symbol $target_CPU_H for target-$target/cpu.h. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Richard Henderson <rth@twiddle.net>
2016-07-12Use #include "..." for our own headers, <...> for othersMarkus Armbruster
Tracked down with an ugly, brittle and probably buggy Perl script. Also move includes converted to <...> up so they get included before ours where that's obviously okay. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Tested-by: Eric Blake <eblake@redhat.com> Reviewed-by: Richard Henderson <rth@twiddle.net>
2016-07-12Fix confusing argument names in some common functionsSergey Sorokin
There are functions tlb_fill(), cpu_unaligned_access() and do_unaligned_access() that are called with access type and mmu index arguments. But these arguments are named 'is_write' and 'is_user' in their declarations. The patches fix the arguments to avoid a confusion. Signed-off-by: Sergey Sorokin <afarallax@yandex.ru> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Message-id: 1465907177-1399402-1-git-send-email-afarallax@yandex.ru Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-07-05ppc/hash64: Fix support for LPCR:ISLBenjamin Herrenschmidt
We need to ignore the segment page size and essentially treat all pages as coming from a 4K segment. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [dwg: Adjusted for differences in my version of the prereq patches] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-07-05ppc/hash64: Add proper real mode translation supportBenjamin Herrenschmidt
This adds proper support for translating real mode addresses based on the combination of HV and LPCR bits. This handles HRMOR offset for hypervisor real mode, and both RMA and VRMA modes for guest real mode. PAPR mode adjusts the offsets appropriately to match the RMA used in TCG, but we need to limit to the max supported by the implementation (16G). This includes some fixes by Cédric Le Goater <clg@kaod.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [dwg: Adjusted for differences in my version of the prereq patches] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-07-05target-ppc: Return page shift from PTEG searchDavid Gibson
ppc_hash64_pteg_search() now decodes a PTEs page size encoding, which it didn't previously do. This means we're now double decoding the page size because we check it int he fault path after ppc64_hash64_htab_lookup() returns. To avoid this duplication have ppc_hash64_pteg_search() and ppc_hash64_htab_lookup() return the page size from the PTE and use that in the callers instead of decoding again. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2016-07-05target-ppc: Simplify HPTE matchingDavid Gibson
ppc_hash64_pteg_search() explicitly checks each HPTE's VALID and SECONDARY bits, then uses the HPTE64_V_COMPARE() macro to check the B field and AVPN. However, a small tweak to HPTE64_V_COMPARE() means we can check all of these bits at once with a suitable ptem value. So, consolidate all the comparisons for simplicity. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2016-07-05target-ppc: Correct page size decoding in ppc_hash64_pteg_search()David Gibson
The architecture specifies that when searching a PTEG for PTEs, entries with a page size encoding that's not valid for the current segment should be ignored, continuing the search. The current implementation does this with ppc_hash64_pte_size_decode() which is a very incomplete implementation of this check. We already have code to do a full and correct page size decode in hpte_page_shift(). This patch moves hpte_page_shift() so it can be used in ppc_hash64_pteg_search() and adjusts the latter's parameters to include a full SLBE instead of just a segment page shift. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2016-07-05ppc: simplify ppc_hash64_hpte_page_shift_noslb()Cédric Le Goater
The segment page shift parameter is never used. Let's remove it. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-07-05ppc: simplify max_smt initialization in ppc_cpu_realizefn()Greg Kurz
kvmppc_smt_threads() returns 1 if KVM is not enabled. Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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