aboutsummaryrefslogtreecommitdiff
path: root/target-ppc
AgeCommit message (Collapse)Author
2016-09-23spapr: Introduce sPAPRCPUCoreClassBharata B Rao
Each spapr cpu core type defines an instance_init routine which just populates the CPU class name. This can be done in the class_init commonly for all core types which simplifies the registration. This is inspired by how PowerNV core types are registered. Certain types of spapr cpu cores ('host' and generic type based on host CPU) are initialized in target-ppc/kvm.c. To convert these type registrations to use class_init, we need to expose spapr_cpu_core_class_init() outside of spapr_cpu_core.c. Commit d11b268e1765 added a generic sPAPR CPU core family type to support cases like POWER8 CPU type on POWER8E host CPU. Switching to class_init would fix such scenarios to use the right CPU thread type instead of defaulting to host-powerpc64-cpu. In an unrelated cleanup, fix a typo in .get_hotplug_handler routine. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-23target-ppc: implement darn instructionRavi Bangoria
darn: Deliver A Random Number Currently return invalid random number for all the case. This needs proper algorithm to provide cryptographically suitable random data. Reading from /dev/random can block and that is not an expected behaviour while the cpu instruction is getting executed. Moreover, /dev/random would only work for linux-user Signed-off-by: Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> [dwg: Added minor clang warning fix for ppc32 target] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-23target-ppc: add stxsi[bh]x instructionNikunj A Dadhania
stxsibx - Store VSX Scalar as Integer Byte Indexed stxsihx - Store VSX Scalar as Integer Halfword Indexed Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-23target-ppc: add lxsi[bw]zx instructionNikunj A Dadhania
lxsibzx - Load VSX Scalar as Integer Byte & Zero Indexed lxsihzx - Load VSX Scalar as Integer Halfword & Zero Indexed Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-23target-ppc: add xxspltib instructionNikunj A Dadhania
xxspltib: VSX Vector Splat Immediate Byte Copy the immediate byte in each byte of target VSR Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-23target-ppc: consolidate store conditionalNikunj A Dadhania
Use tcg_gen_qemu_st store conditional instructions. Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-23target-ppc: move out stqcx impementationNikunj A Dadhania
Being a 16byte operation, qemu_ld/st still does not support this. Move this out so other store operation can use qemu_ld/st in the following patch. Also, convert it to two MO_Q operations for stqcx. Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-23target-ppc: consolidate load with reservationNikunj A Dadhania
Use tcg_gen_qemu_ld in the load with reservation instructions. Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-23target-ppc: convert st[16,32,64]r to use new macroNikunj A Dadhania
Make byte-swap routines use the common GEN_QEMU_STORE macro Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-23target-ppc: convert st64 to use new macroNikunj A Dadhania
Use macro for st64 as well, this changes the function signature from gen_qemu_st64 => gen_qemu_st64_i64. Replace this at all the call sites. Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-23target-ppc: consolidate store operationsNikunj A Dadhania
Implement macro to consolidate store operations using newer tcg_gen_qemu_st function. Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-23target-ppc: convert ld[16,32,64]ur to use new macroNikunj A Dadhania
Make byte-swap routines use the common GEN_QEMU_LOAD macro Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-23target-ppc: convert ld64 to use new macroNikunj A Dadhania
Use macro for ld64 as well, this changes the function signature from gen_qemu_ld64 => gen_qemu_ld64_i64. Replace this at all the call sites. Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-23target-ppc: consolidate load operationsNikunj A Dadhania
Implement macro to consolidate load operations using newer tcg_gen_qemu_ld functions. Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-23target-ppc: add vector permute right indexed instructionRajalakshmi Srinivasaraghavan
Add vpermr instruction from ISA 3.0. Signed-off-by: Rajalakshmi Srinivasaraghavan <raji@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-23target-ppc: add vector bit permute doubleword instructionRajalakshmi Srinivasaraghavan
Add vbpermd instruction from ISA 3.0. Signed-off-by: Rajalakshmi Srinivasaraghavan <raji@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-23target-ppc: add vector count trailing zeros instructionsRajalakshmi Srinivasaraghavan
The following vector count trailing zeros instructions are added from ISA 3.0. vctzb - Vector Count Trailing Zeros Byte vctzh - Vector Count Trailing Zeros Halfword vctzw - Vector Count Trailing Zeros Word vctzd - Vector Count Trailing Zeros Doubleword Signed-off-by: Rajalakshmi Srinivasaraghavan <raji@linux.vnet.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-23target-ppc: add vector extract instructionsRajalakshmi Srinivasaraghavan
The following vector extract instructions are added from ISA 3.0. vextractub - Vector Extract Unsigned Byte vextractuh - Vector Extract Unsigned Halfword vextractuw - Vector Extract Unsigned Word vextractd - Vector Extract Unsigned Doubleword Signed-off-by: Rajalakshmi Srinivasaraghavan <raji@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-23target-ppc: add vector insert instructionsRajalakshmi Srinivasaraghavan
The following vector insert instructions are added from ISA 3.0. vinsertb - Vector Insert Byte vinserth - Vector Insert Halfword vinsertw - Vector Insert Word vinsertd - Vector Insert Doubleword Signed-off-by: Rajalakshmi Srinivasaraghavan <raji@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-23ppc: restrict the use of the rfi instructionBenjamin Herrenschmidt
Power ISA 2.x has deleted the rfi instruction and rfid shoud be used instead on cpus following this instruction set or later. This will raise an invalid exception when rfi is used on such processors: Book3S 64-bit processors. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [clg: the required fix in openbios, commit b747b6acc272 ('ppc: use rfid when running under a CPU from the 970 family.'), is now merged in qemu under commit 5cebd885d0d2 ('Update OpenBIOS images to b747b6a built from submodule.') ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-15Remove unused function declarationsLadi Prosek
Unused function declarations were found using a simple gcc plugin and manually verified by grepping the sources. Signed-off-by: Ladi Prosek <lprosek@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2016-09-07ppc: Improve a few more helper flagsBenjamin Herrenschmidt
Mostly turn "store" type of helpers into TCG_CALL_NO_WG because they can take exceptions. Also fixup_thrm doesn't read nor write the tracked environment. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Improve the exception helpers flagsBenjamin Herrenschmidt
They generate exceptions, but they don't update the environment Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Improve flags for helpers loading/writing the time facilitiesBenjamin Herrenschmidt
Those helpers never load from or store to the TCG tracked environment, not do they generate synchronous exceptions (they might generate an asynchronous interrupt but that's not an issue here). So we can make them all use TCG_CALL_NO_RWG Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Don't generate dead code on unconditional branchesBenjamin Herrenschmidt
We are always generating the "else" case of the condition even when generating an unconditional branch that will never hit it. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Rename #include'd .c files to .inc.cBenjamin Herrenschmidt
Also while at it, group the #include statements in translate.c Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: add extswsli[.] instructionNikunj A Dadhania
extswsli : Extend Sign Word & Shift Left Immediate Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: add vsrv instructionVivek Andrew Sha
Adds Vector Shift Right Variable instruction. Signed-off-by: Vivek Andrew Sha <vivekandrewsha@gmail.com> [ reverse the order of computation to avoid temporary array ] Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: add vslv instructionVivek Andrew Sha
vslv: Vector Shift Left Variable Signed-off-by: Vivek Andrew Sha <vivekandrewsha@gmail.com> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: add vcmpnez[b,h,w][.] instructionsSwapnil Bokade
Adds following instructions: vcmpnezb[.]: Vector Compare Not Equal or Zero Byte vcmpnezh[.]: Vector Compare Not Equal or Zero Halfword vcmpnezw[.]: Vector Compare Not Equal or Zero Word Signed-off-by: Swapnil Bokade <bokadeswapnil@gmail.com> [ collapse switch case ] Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: add vabsdu[b,h,w] instructionsSandipan Das
Adds following instructions: vabsdub: Vector Absolute Difference Unsigned Byte vabsduh: Vector Absolute Difference Unsigned Halfword vabsduw: Vector Absolute Difference Unsigned Word Signed-off-by: Sandipan Das <sandipandas1990@gmail.com> [ use ISA300 define. Drop etype ] Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: add dtstsfi[q] instructionsSandipan Das
DFP Test Significance Immediate [Quad] Signed-off-by: Sandipan Das <sandipandas1990@gmail.com> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: implement branch-less divd[o][.]Nikunj A Dadhania
Similar to divw, implement branch-less divd. Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07target-ppc: implement branch-less divw[o][.]Nikunj A Dadhania
While implementing modulo instructions figured out that the implementation uses many branches. Change the logic to achieve the branch-less code. Undefined value is set to dividend in case of invalid input. Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: load/store multiple and string insns don't do LEBenjamin Herrenschmidt
Just generate an alignment interrupt Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Use a helper to generate "LE unsupported" alignment interruptsBenjamin Herrenschmidt
Some operations aren't allowed in LE mode, use a helper rather than open coding the exception generation. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Don't set access_type on all load/stores on hash64Benjamin Herrenschmidt
We don't use it so let's not generate the updates. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Fix CFAR updatesBenjamin Herrenschmidt
We were one instruction off Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Speed up dcbzBenjamin Herrenschmidt
Use tlb_vaddr_to_host to do a fast path single translate for the whole cache line. Also make the reservation check match the entire range. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Handle unconditional (always/never) traps at translation timeBenjamin Herrenschmidt
We don't need to call a helper for trap always and trap never which are used by Linux under some circumstances. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> -- v2. Don't generate the helper call when trapping always Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Make alignment exceptions suck lessBenjamin Herrenschmidt
The current alignment exception generation tries to load the opcode to put in DSISR from a context where a cpu_ldl_code() is really not a good idea. It might fault and longjmp out and that's not something we want happening here. Instead, pass the releavant opcode bits via the error_code. There are a couple of cases of alignment interrupts that won't set anything, the ones coming from access to direct store segments, but that doesn't happen in practice, nobody used direct store segments and they are gone from newer chips. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Don't update NIP in dcbz and lscbxBenjamin Herrenschmidt
Instead, pass GETPC() result to the corresponding helpers. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Don't update NIP if not taking alignment exceptionsBenjamin Herrenschmidt
Move the NIP update to after the conditional branch so that we don't do it if we aren't going to take the alignment exception Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Don't update NIP on conditional trap instructionsBenjamin Herrenschmidt
This is no longer necessary as the helpers will properly retrieve the return address when needed. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Don't update NIP BookE 2.06 tlbweBenjamin Herrenschmidt
This is no longer necessary as the helpers will properly retrieve the return address when needed. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Don't update NIP in facility unavailable interruptsBenjamin Herrenschmidt
This is no longer necessary as the helpers will properly retrieve the return address when needed. Also remove gen_update_current_nip() which didn't seem to make much sense to me. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Don't update NIP in DCR access routinesBenjamin Herrenschmidt
This is no longer necessary as the helpers will properly retrieve the return address when needed Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Fix source NIP on SLB related interruptsBenjamin Herrenschmidt
We need to pass it to the raise helper since we don't update it before the calls. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Make tlb_fill() use new exception helperBenjamin Herrenschmidt
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-09-07ppc: Don't update NIP in lmw/stmw/icbiBenjamin Herrenschmidt
Instead, pass GETPC() result to the corresponding helpers. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
generated by cgit v1.2.3 (git 2.26.2) at 2024-12-17 11:14:40 +0000