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2009-07-13target-ppc: enable PPC_MFTB for 44xBaojun Wang
According to PPC440 user manual, PPC 440 supports ``mftb'' even it's a preserved instruction: PPC440_UM2013.pdf, p.445, table A-3 when I compile a kernel (2.6.30, bamboo_defconfig/440EP & canyonlands/460EX), I can see ``mftb'' by using ppc-xxx-objdump vmlinux I have also checked the ppc 440x[456], 460S, 464, they also should support mftb. The following patch enable mftb for all ppc 440 variants, including: 440EP, 440GP, 440x4, 440x5 and 460 Signed-off-by: Baojun Wang <wangbj@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-07-13ppc tcg: fix wrong bit/mask of wrteeiBaojun Wang
Signed-off-by: Baojun Wang <wangbj@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-07-12target-ppc: fix evmergelo and evmergelohiNathan Froyd
For 32-bit PPC targets, we translated: evmergelo rX, rX, rY as: rX-lo = rY-lo rX-hi = rX-lo which is wrong, because we should be transferring rX-lo first. This problem is fixed by swapping the order in which we write the parts of rX. Similarly, we translated: evmergelohi rX, rX, rY as: rX-lo = rY-hi rX-hi = rX-lo In this case, we can't swap the assignment statements, because that would just cause problems for: evmergelohi rX, rY, rX Instead, we detect the first case and save rX-lo in a temporary variable: tmp = rX-lo rX-lo = rY-hi rX-hi = tmp These problems don't occur on PPC64 targets because we don't split the SPE registers into hi/lo parts for such targets. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-06-23target-ppc: permit linux-user to read PVRNathan Froyd
Access to the PVR SPR is normally forbidden from userspace apps. The Linux kernel, however, fixes up reads in the appropriate trap handler. To permit applications that read PVR to run on QEMU, then, we need to implement the same handling of PVR reads. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: malc <av1474@comtv.ru>
2009-06-20Apply TCGV_UNUSED on variables that GCC mistakenly thinks can be usedmalc
uninitialized
2009-06-17Replace ELF section hack with normal tableBlue Swirl
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-06-17Concentrate rest of table entries to topBlue Swirl
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-06-17Concentrate most table entries to topBlue Swirl
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-06-17Clean up GEN_HANDLER2Blue Swirl
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-06-17Clean up GEN_HANDLERBlue Swirl
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-06-13Fix mingw32 build warningsBlue Swirl
Work around buffer and ioctlsocket argument type signedness problems Suppress a prototype which is unused on mingw32 Expand a macro to avoid warnings from some GCC versions Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-05-22kvm: Add missing bits to support live migrationJan Kiszka
This patch adds the missing hooks to allow live migration in KVM mode. It adds proper synchronization before/after saving/restoring the VCPU states (note: PPC is untested), hooks into cpu_physical_memory_set_dirty_tracking() to enable dirty memory logging at KVM level, and synchronizes that drity log into QEMU's view before running ram_live_save(). Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-05-21Convert machine registration to use module init functionsAnthony Liguori
This cleans up quite a lot of #ifdefs, extern variables, and other ugliness. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-05-19Hardware convenience libraryPaul Brook
The only target dependency for most hardware is sizeof(target_phys_addr_t). Build these files into a convenience library, and use that instead of building for every target. Remove and poison various target specific macros to avoid bogus target dependencies creeping back in. Big/Little endian is not handled because devices should not know or care about this to start with. Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-05-16target-ppc: expose cpu capability flagsNathan Froyd
Do this so other pieces of code can make decisions based on the capabilities of the CPU we're emulating. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: malc <av1474@comtv.ru>
2009-05-13Include assert.h from qemu-common.hPaul Brook
Include assert.h from qemu-common.h and remove other direct uses. cpu-all.h still need to include it because of the dyngen-exec.h hacks Signed-off-by: Paul Brook <paul@codesourcery.com>
2009-05-13Fix typo that leads to out of bounds array access on big endian systemsmalc
2009-04-28Fix powerpc 604 reset vectorTristan Gingold
According to 604eUM_book (see 8.3.3 Reset inputs p8-54), the IP bit is set for hreset and the vector is at offset 0x100 from the exception prefix. No difference in this area between 604 and 604e. Signed-off-by: Tristan Gingold <gingold@adacore.com>
2009-04-28Fix PPC resetBlue Swirl
2009-04-24qemu: introduce qemu_init_vcpu (Marcelo Tosatti)aliguori
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7242 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-24qemu: per-arch cpu_has_work (Marcelo Tosatti)aliguori
Blue Swirl: fix Sparc32 breakage Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7238 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-16target-ppc: mark a few helpers TCG_CALL_CONST and/or TCG_CALL_PUREaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7129 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-13Fix ppc-softmmu warnings on OpenBSD hostblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7099 c046a42c-6fe2-441c-8c8c-71466251a162
2009-04-05Add new command line option -singlestep for tcg single stepping.aurel32
This replaces a compile time option for some targets and adds this feature to targets which did not have a compile time option. Add monitor command to enable or disable single step mode. Modify monitor command "info status" to display single step mode. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7004 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-29target-ppc: Explain why the whole TLB is flushed on SR writeaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6947 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-29target-ppc: avoid nop to override next instructionaurel32
While searching PC, always store the pc of a new instruction. Instructions that didn't generate tcg code (such as nop) prevented the next one to be referenced. Based on patch for target-alpha, r6930. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6931 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-13Make the ELF loader aware of backwards compatibilityblueswir1
Most 64 bit architectures I'm aware of support running 32 bit code of the same architecture as well. So x86_64 can run i386 code easily and ppc64 can run ppc code. Unfortunately, the current checks are pretty strict. So you can only load e.g. an x86_64 elf binary on qemu-system-x86_64, but no i386 one. This can get really annoying. I first encountered this issue with my multiboot patch, where qemu-system-x86_64 was unable to load an i386 elf binary because the elf loader rejected it. The same thing happened again on PPC64 now. The firmware we're loading is a PPC32 elf binary, as it's shared with PPC32. But the platform is PPC64. Right now there is a hack for this in the ppc cpu.h definition, that simply sets the type to PPC32 in system emulation mode. While that works fine for the firmware, it's no good if you also want to load a PPC64 kernel with -kernel. So in order to solve this mess, I figured the easiest way is to make the elf loader aware of platforms that are backwards compatible. For now I was only sure that x86_64 does i386 and ppc64 does ppc32, but maybe there are other combinations too. This patch is a prerequisite for having a working -kernel option on PPC64. Signed-off-by: Alexander Graf <alex@csgraf.de> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6855 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-13target-ppc: use the new bswap* TCG opsaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6835 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-13tcg: rename bswap_i32/i64 functionsaurel32
Rename bswap_i32 into bswap32_i32 and bswap_i64 into bswap64_i64 Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6829 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-10target-ppc: fix commit r6789aurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6804 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-09targe-ppc: optimize mfcr and mtcrfaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6793 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-09target-ppc: free a tcg temp variableaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6790 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-09target-ppc: add support for reading/writing spefscraurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6789 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-07Fix off-by-one errors for Altivec and SPE registersaurel32
Altivec and SPE both have 34 registers in their register sets, not 35 with a missing register 32. GDB would ask for register 32 of the Altivec (resp. SPE) registers and the code would claim it had zero width. The QEMU GDB stub code would then return an E14 to GDB, which would complain about not being sure whether p packets were supported or not. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6769 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-07Disable BAT for 970blueswir1
The 970 doesn't know BAT, so let's not search BATs there. This was only in as a hack for OpenHackWare so it would work on PPC64. Signed-off-by: Alexander Graf <alex@csgraf.de> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6759 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-07Fix mfcr on ppc64-softmmuaurel32
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6758 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-07Keep SLB in-CPUblueswir1
Real 970 CPUs have the SLB not memory backed, but inside the CPU. This breaks bridge mode for 970 for now, but at least keeps us from overwriting physical addresses 0x0 - 0x300, rendering our interrupt handlers useless. I put in a stub for bridge mode operation that could be enabled easily, but for now it's safer to leave that off I guess (970fx doesn't have bridge mode AFAIK). Signed-off-by: Alexander Graf <alex@csgraf.de> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6757 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-07Fix NX bitblueswir1
ctx->nx only got ORed, but never reset. So when one page in the lifetime of the VM was ever NX, all later pages were too. Signed-off-by: Alexander Graf <alex@csgraf.de> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6755 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-07Fix RFI(d)blueswir1
The current implementation masks some MSR bits from SRR1 as it is given on rfi(d). This looks pretty wrong and breaks Altivec. Signed-off-by: Alexander Graf <alex@csgraf.de> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6754 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-07Implement mtfsf.L encodingblueswir1
Mtfsf can have the L bit set, so all the register contents get stored in FPSCR. Linux uses it, so let's implement it. Signed-off-by: Alexander Graf <alex@csgraf.de> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6753 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-07Enable 64bit mode on interruptsblueswir1
Real 970s enable MSR_SF on all interrupts. The current code didn't do this until now, so let's activate it! Signed-off-by: Alexander Graf <alex@csgraf.de> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6752 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-07Nop some SPRs on 970fxblueswir1
Linux tries to access some SPRs on PPC64 boot. Let's just ignore those for the 970fx for now to make it happy. Signed-off-by: Alexander Graf <alex@csgraf.de> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6751 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-07Implment tlbielblueswir1
Linux uses tlbiel to flush TLB entries in PPC64 mode. This special TLB flush opcode only flushes an entry for the CPU it runs on, not across all CPUs in the system. Signed-off-by: Alexander Graf <alex@csgraf.de> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6749 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-07Implement large pagesblueswir1
The current SLB/PTE code does not support large pages, which are required by Linux, as it boots up with the kernel regions up as large. This patch implements large page support, so we can run Linux. Signed-off-by: Alexander Graf <alex@csgraf.de> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6748 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-07Implement slbmteblueswir1
In order to modify SLB entries on recent PPC64 machines, the slbmte instruction is used. This patch implements the slbmte instruction and makes the "bridge" mode code use the slb set functions, so we can move the SLB into the CPU struct later. This is required for Linux to run on PPC64. Signed-off-by: Alexander Graf <alex@csgraf.de> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6747 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-07Sparse fixes: add extern to ELF opcode tables to avoid warningsblueswir1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6740 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-07The _exit syscall is used for both thread termination in NPTL applications,pbrook
and process termination in legacy applications. Try to guess which we want based on the presence of multiple threads. Also implement locking when modifying the CPU list. Signed-off-by: Paul Brook <paul@codesourcery.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6735 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-03target-ppc: improve mfcr/mtcrfaurel32
- use ctz32 instead of ffs - 1 - small optimisation of mtcrf - add the name of both opcodes Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6669 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-02Fix mtcrf/mfcrmalc
Noticed by Alexander Graf git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6667 c046a42c-6fe2-441c-8c8c-71466251a162
2009-03-02kvm/powerpc: Add MPC8544DS board supportaurel32
This patch add an emulation of MPC8544DS board. It can work on All E500 platforms. Signed-off-by: Liu Yu <yu.liu@freescale.com> Acked-by: Hollis Blanchard <hollisb@us.ibm.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6663 c046a42c-6fe2-441c-8c8c-71466251a162
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